DAC8412ATSLASH883C datasheet(5/20 Pages) AD

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Data Sheet

DAC8412/DAC8413

Rev. G | Page 5 of 20

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Write Data Setup

tWDS

tWCS = 150 ns

Write Data Hold

tWDH

tWCS = 150 ns

Load Data Pulse Width

tLDW

180

Reset Pulse Width

tRESET

150

Chip Select Read Pulse Width

tRCS

170

Read Data Hold

tRDH

tRCS = 170 ns

Read Data Setup

tRDS

tRCS = 170 ns

Data to High-Z

tDZ

CL = 10 pF

200

Chip Select to Data

tCSD

CL = 100 pF

320

SUPPLY CHARACTERISTICS

Power Supply Sensitivity

PSS

100

ppm/V

Positive Supply Current

IDD

Negative Supply Current

ISS

VSS = −5.0 V

−10

Power Dissipation

PDISS

VSS = 0 V

VSS = −5.0 V

110

1 All supplies can be varied ±5%, and operation is guaranteed. Device is tested with VDD = 4.75 V.

2 For single-supply operation only (VREFL = 0.0 V, VSS = 0.0 V). Due to internal offset errors, INL and DNL are measured beginning at 0x005.

3 Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.

4 All parameters are guaranteed by design.

5 All input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

A0/A1

tRDS

tRCS

tRDH

tAS

tAH

tDZ

tCSD

R/W

DATA

OUT

DATA VALID

HIGH-Z

Figure 3. Data Output (Read Timing)

A0/A1

RESET

LDAC

tWCS

R/W

DATA IN

tWS

tWH

tAS

tAH

tLS

tLH

tWDH

tWDS

tLDW

tRESET

Figure 4. Data Write (Input and Output Registers) Timing

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