ISL6590DR datasheet(13/24 Pages) INTERSIL

13 / 24 page

Backside Serial Bus (BSB)

The transfer of data on the BSB consists of a start bit, 5 ID

bits, 5 memory address bits, a read/write bit, an address

acknowledge bit, 8 data bits, a data acknowledge bit, and a

stop bit. The rate of transfer is set by the serial clock divider

Background polling of ISL6580 fault registers is performed

using the BSB. The fault information is written to the

ISL6590 local copies of the ISL6580 fault registers. ISL6580

control registers can be written to or read back from the

ISL6590 memory via the BSB.

Startup Process

ISL6580 Enumeration

After power-up of the system, each installed ISL6580 is

polled for its existence. This procedure involves the

Controller to assert the PWM signal for a specific Power IC.

If the specified Power IC is present, it will assert its signal to

acknowledge seeing its PWM asserted. This sequence is

repeated for each Power IC that may be in the system. This

process is known as Device Polling.

After this initial PWM polling is complete, the serial interface

of each Power IC has to be configured with a device ID to be

able to respond to serial commands later. This procedure

involves issuing a “config call” which is to send a serial write

command to global device ID ‘0’. During the data portion of

the cycle, the Power IC to be configured has its PWM signal

asserted by the Controller. This action allows the data bits

that are sent from the Controller to be shifted into a device ID

Enumeration.

During enumeration, the address on the serial bus for each

ISL6580 is uniquely defined according to Table 6. If an

address acknowledge bit is not returned, the device is not

used because it is either not present or not functional. The

PWM signals are used to enable address writing to each

ISL6580. Fault processing is disabled during enumeration.

MEMORY

BUS

MUX

MEMORY

STATE

CONTROL/

FAULT

MONITOR

READ

ADDR[15:0]

DATA[7:0]

ADDR[15:0]

WRITE

DONE

OPEN LOOP

READ

WRITE

ASYNCHRONOUS

SERIAL

INTERFACE

(ASI)

(REGISTERS)

FEEDBACK

CONTROL

BACKSIDE

SERIAL

BUS

EEPROM

INTERFACE

STATUS

COEFFICIENTS

CONTROL

STATUS

DONE

WRITE

DATA[7:0]

ADDR[4:0]

DEVICE[4:0]

MDI

/MCS

MCLK

MDO

CONTROL

AND

STATUS

REGISTERS

EEPROM

INTERFACE

ISL6580

MAPPED

REGISTERS

ATX

ARX

PWRGD

OUTEN

VID[5:0]

FIGURE 10. MEMORY INTERFACE DIAGRAM

ISL6590

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