2

Block Diagram

Simplified Power System Diagram

Functional Pin Description

VID3 (Pin 1), VID2 (Pin 2), VID1 (Pin 3), VID0 (Pin 4)

and VID25mV (Pin 5)

Voltage Identification inputs from microprocessor. These pins

respond to TTL and 3.3V logic signals. The ISL6562 decodes

VID bits to establish the output voltage. See Table 1.

COMP (Pin 6)

Output of the internal transconductance error amplifier.

Voltage at this terminal sets the output current level of the

Current Sense Comparator. Pulling this pin to ground

disables the oscillator and drives both PWM outputs low.

FB (Pin 7)

Inverting input of the internal transconductance error

amplifier.

CT (Pin 8)

A capacitor on this terminal sets the frequency of the internal

oscillator.

GND (Pin 9)

Bias and reference ground. All signals are referenced to this

pin.

PWRGD (Pin 10)

Open drain connection. A high voltage level at this pin with a

resistor connected to this terminal and VCC indicates that

CORE voltage is at the proper level,

supply current to the converter positive input voltage. CS+ is

connected directly to the decoupled supply voltage and

current sampling resistor. CS- is connected to the other end

of the current sampling resistor and the upper drains of the

series transistors.

PWM2 (Pin 12) and PWM1 (Pin 13)

PWM outputs connected to the gate driver ICs.

REF (Pin 15)

Three volt supply used to bias the output of the

transconductance amplifier.

VCC (Pin 16)

Bias supply. Connect this pin to a 12V supply.

D/A

UV

OVP

E/A

CMP

PWM1

PWM2

CS+

CS-

GND

REF

VCC

FB

VID3

VID2

VID1

VID0

VID25mV

COMP

OSCILLATOR

X1.24

PWRGD

3V REFERENCE

BIAS CIRCUITS

UVLO and

CT

CONTROL

LOGIC

+

-

+

-

+

-

X 0.82

+

-

SYNCHRONOUS

ISL6562

MICROPROCESSOR

FB

VID

RECTIFIED BUCK

CHANNEL

SYNCHRONOUS

RECTIFIED BUCK

CHANNEL

PWM 1

PWM 2

VID3

VID2

VID1

VID0

VID25mV

CT

PWRGD

REF

PWM1

PWM2

VCC

FB

CS-

COMP

CS+

GND

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

ISL6562