RNA52A10MM datasheet(9/12 Pages) RENESAS

9 / 12 page

RNA52A10MM

REJ03D0858-0500 Rev.5.00 Oct 06, 2008

Page 7 of 11

Pin Descriptions

Pin No.

Pin Name

Function

Manual reset input pin for reset circuit 2 (the circuit with the delay function).

The MR signal is active high, so applying a high level to MR sets the Vo2 pin to the low level.

If Vi2

> V

REF when the signal on the MR pin is changed back from the high to the low level, the Vo2 pin is returned

from the low to the high level after a delay time TDLY0. This can be set as required. The MR pin is pulled down to

the GND level via an internal 2-M

Ω resistor . However, we recommend connection of the pin to the GND line

when it is not in use.

Vo1

Reset signal output pin for reset circuit 1 (the circuit with no delay function). The output is open-drain.

The recommended value of the pull-up resistor (RL1) is 3 k to 100 k

Ω. When the voltage input on pin Vi1 falls to or

below VREF, the signal output from the Vo1 pin is changed from the high to the low level. Since the characteristic

includes hysteresis, the signal output from the

Vo1 pin changes from the low to the high level when the voltage

input on pin Vi1 rises to or above VREF+VHYS. Refer to the timing diagram on page 4 for details.

Vo2

Reset signal output pin for reset circuit 2 (the circuit with the delay function). The output is open-drain.

The recommended value for the pull-up resistor (RL2 ) is 3 k to 100 k

Ω. When the voltage input on pin Vi2 falls to

or below VREF, the signal output from the Vo2 pin is changed from the high to the low level. Since the input

characteristic includes hysteresis, the signal output from the

Vo2 pin changes from the low to the high level when

the voltage input on pin Vi2 rises to or above VREF+VHYS and the set delay time TDLY0 has elapsed. Refer to the

timing diagram on page 4 and regulations for state of capacitor CD electrical discharge and delay time on page 10

for details.

GND

GND pin

Pin for connection to the resistor (RD) and capacitor (CD) for setting of the delay time, TDLY0. Refer to the Block

Diagram and Typical Application Circuit on page 2 for an example of the connection. The relation by which the

resistance and capacitance set up the delay time can be expressed as TDLY0 = 0.94

× C

× R

D. Refer to this

formula in determining the values of resistance and capacitance. Resistance RD must use the one within the

range of 1 k to 1 M

Ω. Ensure that capacitor C

D has a value no greater than 1.3

µF. The dependence of delay

time TDLY0 on the values of external capacitor CD and external resistor RD is illustrated on page 10. To avoid errors

due to noise input via the CD pin, this input includes a Schmitt-trigger inverter.

Vi2

Voltage input pin for reset circuit 2 (the circuit with the delay function). When the input voltage falls to or below

VREF, the signal output from the Vo2 pin is changed to the low level. Since the input characteristic includes

hysteresis, the signal output from the

Vo2 pin is changed from the low to the high level after the voltage input on

pin Vi2 has risen to or above VREF+VHYS and delay time TDLY has elapsed. The reset-threshold voltage is derived

from the power-supply voltage VDD2 according to the division ratio set up by resistors RS3 and RS4 as described

under the block diagram and typical application circuit on page 3. To avoid shifting of the reset detection voltage

being shifted by input current via the Vi2 pin, select a value no greater than 25 k

Ω for parallel resistors R

S3 and

RS4. Refer to the graph on page 3 for details. Besides, to avoid errors due to noise in power-supply voltage VDD2,

select a capacitor with superior frequency characteristics and connect it between the Vi2 and GND pins.

Vi1

Voltage input pin for reset circuit 1 (the circuit without the delay function). When the input voltage falls to or below

VREF, the signal output from the Vo1 pin is changed to the low level. Since the input characteristic includes

hysteresis, the signal output from the

Vo1 pin is changed from the low to the high level after the voltage input on

pin Vi1 has risen to or above VREF+VHYS. The reset-threshold voltage is derived from the power-supply voltage

VDD1 according to the division ratio set up by resistors RS1 and RS2 as described under the block diagram and

typical application circuit on page 3. To avoid shifting of the reset detection voltage being shifted by input current

via the Vi1 pin, select a value no greater than 25 k

Ω for parallel resistors R

S1 and RS2. Refer to the graph on page

3 for details. Besides, to avoid errors due to noise in power-supply voltage VDD1, select a capacitor with superior

frequency characteristics and connect it between the Vi2 and GND pins.

VDD

Power-supply pin for the chip. For stable operation, select a capacitor with superior frequency characteristics

and connect it between the VDD and GND pins and as close to the chip as possible. When selecting the value of

the capacitor, consider aspects of the system environment such as the quality of the power supply. Refer to the

block diagram and typical application circuit on page 3 for details.

RNA52A10MM датащи(PDF) 9 Page - Renesas Technology Corp

RNA52A10MM датащи(HTML) 9 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12

датащи скачать

ссылки URL