7-68

December 1996

HSP50307

Burst QPSK Modulator

Features

• 256 KBPS Data Rate and 128 KBPS Baud Rate

• Burst QPSK Modulation

• Programmable Carrier Frequency from 8MHz to

15MHz With a Frequency Step Size of 32kHz

•

α = 0.5 Root Raised Cosine (RRC) Filtering For Spec-

trum Shaping

• On-Board Synthesizer

• Programmable Output Level From 22 to 62dBmV in

1dB Steps

• Programmable Charge Pump Current Control

• 62dBmV Differential Output Driver for 75

Ω Cable

Applications

• Burst QPSK Modulator

• HSP50307EVAL1 Evaluation Board Is Available

Description

The HSP50307 is a mixed signal burst QPSK Modulator for

upstream CATV Applications. The HSP50307 demultiplexes

and modulates a serial data stream onto an RF Carrier cen-

tered between 8 and 15MHz. The signal spectrum is shaped

with

α = 0.5 root raised cosine (RRC) digital filters. On-chip fil-

tering limits spurs and harmonics to levels below -35dBc dur-

ing transmissions. The output power level is adjustable over a

40dB range in 1dB steps. The maximum differential output

level is +62dBmV into 75

Ω. A transmitter inhibit function dis-

ables the RF output outside the burst interval. The differential

output amplifier int7-erfaces to the cable via a transformer.

The Block Diagram of the HSP50307 QPSK Modulator is

shown below. The HSP50307 consists of a digital control

interface, an I/Q generator, a synthesizer, and a quadrature

modulator.

The data clock is derived from the master clock. The

HSP50307 demultiplexes the input data bits into in-phase (I)

and quadrature (Q) data streams. The first bit and subsequent

alternating bits of the burst are in-phase data. The two data

streams are filtered, converted from digital to analog, and low

pass filtered to produce the baseband I and Q analog signals.

The baseband signals are up-converted to RF in the Quadra-

ture Modulation Section. The synthesizer provides the local

oscillator (LO) for the quadrature modulator. The frequency is

programmable via the control interface with a resolution of

32kHz. The output of the quadrature modulator is low pass fil-

tered to remove harmonic distortion.

Block Diagram

Ordering Information

PART NUMBER

TEMP.

PACKAGE

PKG.

NO.

HSP50307SC

0 to 70

28 Ld SOIC

M28.3

LPF

CONTROL

INTERFACE

RESET

MCLK

TXCLK

TX_DATA

TX_EN

C_EN

CCLK

CDATA

TX_EN

I

Q

8RRC

LPF

8RRC

9

9

QUAD

GEN

VCO_SET PD_OUT

SYNTHESIZER

/100

VCO_IN

RCLK

LPF

PGA

MOD_OUT-

+

DAC_REF

VCM_REF

MCLK MUST ALWAYS BE PRESENT FOR PROPER OPERATION

MOD_OUT+

†

†

I/Q GENERATOR

D/A

D/A

QUADRATURE

MODULATOR

†

File Number

4219

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207