HIP7010P datasheet(3/20 Pages) INTERSIL

3 / 20 page

Absolute Maximum Ratings

Thermal Information

Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +7.0V

Input or Output Voltage

Pins with VDD Diode . . . . . . . . . . . . . . . . . . . .-0.3V to VDD +0.3V

Pins without VDD Diode . . . . . . . . . . . . . . . . . . . . -0.3V to +10.0V

ESD Classiﬁcation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2500 Gates

Thermal Resistance

θJA

Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . .+100oC/W

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+120oC/W

Maximum Package Power Dissipation at +125oC

DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250mW

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mW

Operating Temperature Range (TA) . . . . . . . . . . . -40

oC to +125oC

Storage Temperature Range (TSTG). . . . . . . . . . . -65

oC to +150oC

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC

Lead Temperature (Soldering, 10s). . . . . . . . . . . . . . . . . . . . +265oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

Operating Conditions

Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +3.0V to +5.5V

Operating Temperature Range . . . . . . . . . . . . . . . . -40oC to +125oC

Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V

Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .(0.8VDD) to VDD

Input Rise and Fall Time

CMOS Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ns Max

CMOS Schmitt Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . .Unlimited

Electrical Speciﬁcations

TA = -40

oC to +125oC, V

DD = 5VDC ±10%, Unless Otherwise Speciﬁed

PARAMETERS

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Supply Current

Operating Current

IOP

CLK = 2.0 MHz

1.0

5.0

Power-Down Mode (Note 1)

IPD

PD = 1

150

µA

Clock Stopped (Note 2)

ISTOP

CLK = VSS or VDD

5.0

µA

Input High Voltage

CMOS Level (SIN, STAT, RDY, TEST)

VIH

0.7VDD

-VDD

Schmitt Trigger (RESET, CLK, VPWIN)

0.8VDD

-VDD

Input Low Voltage

CMOS Level (SIN, STAT, RDY, TEST)

VIL

VSS

0.3VDD

Schmitt Trigger (RESET, CLK, VPWIN)

VSS

0.2VDD

High Level Input Current

(CLK, VPWIN, RESET)

IIH

VIN = VDD

-1

0.001

µA

Input Buffer with Pull-Down (SIN, TEST, STAT, RDY)

100

200

500

µA

Low Level Input Current

(CLK, VPWIN, RESET)

IIL

VIN = VSS

-1

-0.001

µA

Input Buffer with Pull-Down (SIN, TEST, STAT, RDY)

-10

-0.01

µA

Output High Voltage

(SCK, SOUT, VPWOUT, IDLE, SACTIVE)

VOH

ILOAD = 0.8 mA

VDD-0.8

Output Low Voltage

(SCK, SOUT, VPWOUT, IDLE, SACTIVE)

VOL

ILOAD = -1.6 mA

0.4

High Impedance Leakage Current

Three-State with Pull-Down (SCK, SOUT)

IOZ

VOUT = VDD

100

200

500

µA

VOUT = VSS

-10

µA

Schmitt Trigger Hysteresis Voltage

(RESET, CLK, VPWIN)

VHYS

0.2

0.5

2.0

NOTES:

1. SIN, STAT, RDY, and TEST = VSS; SACTIVE, SCK, and SOUT unconnected; VPWIN = VDD; CLK = 10MHz.

2. SIN, STAT, RDY, and TEST = VSS; SACTIVE, SCK, and SOUT unconnected; VPWIN = VDD; PD = 1.

HIP7010

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