2-306

Layout Considerations

MOSFETs switch very fast and efficiently. The speed with

which the current transitions from one device to another

causes voltage spikes across the interconnecting

impedances and parasitic circuit elements. The voltage

spikes can degrade efficiency, radiate noise into the circuit,

and lead to device over-voltage stress. Careful component

layout and printed circuit design minimizes the voltage

spikes in the converter. Consider, as an example, the turn-

off transition of the upper PWM MOSFET. Prior to turn-off,

the upper MOSFET was carrying the full load current.

During the turn-off, current stops flowing in the upper

MOSFET and is picked up by the lower MOSFET or

Schottky diode. Any inductance in the switched current

path generates a large voltage spike during the switching

interval. Careful component selection, tight layout of the

critical components, and short, wide circuit traces minimize

the magnitude of voltage spikes. See the Application Note

ANTBD for evaluation board drawings of the component

placement and printed circuit board.

There are two sets of critical components in a DC-DC

converter using a HIP6020 controller. The switching power

components are the most critical because they switch large

amounts of energy, and as such, they tend to generate

equally large amounts of noise. The critical small signal

components are those connected to sensitive nodes or

those supplying critical bypass current.

The power components and the controller IC should be

placed first. Locate the input capacitors, especially the high-

frequency ceramic decoupling capacitors, close to the power

switches. Locate the output inductor and output capacitors

between the MOSFETs and the load. Locate the PWM

controller close to the MOSFETs.

The critical small signal components include the bypass

these components close to their connecting pins on the

control IC. Minimize any leakage current paths from SS

node, since the internal current source is only 28

µA.

A multi-layer printed circuit board is recommended. Figure

8shows the connections of the critical components in the

represent numerous physical capacitors. Dedicate one

solid layer for a ground plane and make all critical

component ground connections with vias to this layer.

Dedicate another solid layer as a power plane and break

this plane into smaller islands of common voltage levels.

The power plane should support the input power and

output power nodes. Use copper filled polygons on the top

and bottom circuit layers for the PHASE nodes, but do not

unnecessarily oversize these particular islands. Since the

PHASE nodes are subjected to very high dV/dt voltages,

the stray capacitor formed between these islands and the

surrounding circuitry will tend to couple switching noise.

Use the remaining printed circuit layers for small signal

wiring. The wiring traces from the control IC to the

MOSFET gate and source should be sized to carry 2A

peak currents.

PWM Controller Feedback Compensation

The PWM controller uses voltage-mode control for output

regulation. This section highlights the design consideration

for a PWM voltage-mode controller. Apply the methods and

considerations only to the PWM controller.

Figure 9 highlights the voltage-mode control loop for a

synchronous-rectified buck converter. The output voltage

reference voltage level is the DAC output voltage (DACOUT).

with the oscillator (OSC) triangular wave to provide a pulse-

the PHASE node. The PWM wave is smoothed by the output

The modulator transfer function is the small-signal transfer

Modulator Break Frequency Equations

The compensation network consists of the error amplifier

a closed loop transfer function with high 0dB crossing

180 degrees. The equations below relate the compensation

network’s poles, zeros and gain to the components (R1, R2,

R3, C1, C2, and C3) in Figure 8. Use these guidelines for

locating the poles and zeros of the compensation network:

1. Pick Gain (R2/R1) for desired converter bandwidth

6. Check Gain against Error Amplifier’s Open-Loop Gain

7. Estimate Phase Margin - Repeat if Necessary

F

LC

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ESR

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HIP6021