HIP6003 datasheet(7/12 Pages) INTERSIL

7 / 12 page

Application Guidelines

Layout Considerations

As in any high frequency switching converter, layout is very

important. Switching current from one power device to

another can generate voltage transients across the

impedances of the interconnecting bond wires and circuit

traces. These interconnecting impedances should be

minimized by using wide, short printed circuit traces. The

critical components should be located as close together as

possible using ground plane construction or single point

grounding.

Figure 6 shows the critical power components of the

converter. To minimize the voltage overshoot the

interconnecting wires indicated by heavy lines should be

part of ground or power plane in a printed circuit board. The

components shown in Figure 6 should be located as close

together as possible. Please note that the capacitors CIN

and CO each represent numerous physical capacitors.

Locate the HIP6003 within 3 inches of the MOSFET, Q1.

The circuit traces for the MOSFETs gate and source

connections from the HIP6003 must be sized to handle up to

1A peak current.

Figure 7 shows the circuit traces that require additional

layout consideration. Use single point and ground plane

construction for the circuits shown. Minimize any leakage

current paths on the SS PIN and locate the capacitor, CSS

close to the SS pin because the internal current source is

only 10

µA. Provide local VCC decoupling between VCC and

GND pins. Locate the capacitor, CBOOT as close as practical

to the BOOT and PHASE pins.

Feedback Compensation

Figure 8 highlights the voltage-mode control loop for a buck

converter. The output voltage (VOUT) is regulated to the

Reference voltage level. The error ampliﬁer (Error Amp)

output (VE/A) is compared with the oscillator (OSC)

triangular wave to provide a pulse-width modulated (PWM)

wave with an amplitude of VIN at the PHASE node. The

PWM wave is smoothed by the output ﬁlter (LO and CO).

The modulator transfer function is the small-signal transfer

function of VOUT/VE/A. This function is dominated by a DC

Gain and the output ﬁlter (LO and CO), with a double pole

break frequency at FLC and a zero at FESR. The DC Gain of

the modulator is simply the input voltage (VIN) divided by the

peak-to-peak oscillator voltage

∆VOSC.

UGATE

PHASE

VIN

VOUT

RETURN

HIP6003

CIN

FIGURE 6. PRINTED CIRCUIT BOARD POWER AND

GROUND PLANES OR ISLANDS

+12V

HIP6003

GND

VCC

BOOT

VOUT

PHASE

+VIN

CBOOT

CVCC

CSS

FIGURE 7. PRINTED CIRCUIT BOARD SMALL SIGNAL

LAYOUT GUIDELINES

VOUT

OSC

REFERENCE

ESR

VIN

∆VOSC

ERROR

AMP

PWM

DRIVER

(PARASITIC)

ZFB

DACOUT

COMP

VOUT

ZFB

HIP6003

ZIN

COMPARATOR

DETAILED COMPENSATION COMPONENTS

PHASE

VE/A

ZIN

FIGURE 8. VOLTAGE - MODE BUCK CONVERTER

COMPENSATION DESIGN

HIP6003

HIP6003 датащи(PDF) 7 Page - Intersil Corporation

HIP6003 датащи(HTML) 7 Page - Intersil Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12

датащи скачать

ссылки URL