HIP4083AP datasheet(4/10 Pages) INTERSIL

4 / 10 page

Pin Descriptions

NUMBER

SYMBOL

DESCRIPTION

AHB

BHB

CHB

(xHB)

Gate driver supplies. One external bootstrap diode and one capacitor are required for each. The bootstrap

diode and capacitor may be omitted when the HIP4083 is used to drive the lower gates in three phase full

bridge applications. In this case, tie all three xHB pins to VDD and tie the xHS pins to the sources of the

lower FETs. In full bridge applications, the lower FETs must be turned on ﬁrst at start up to refresh the boot-

strap capacitors. In high side switch applications, the load will keep xHS low and refresh should happen

automatically at start up.

AHI

BHI

CHI

(xHI)

Logic level inputs. Logic at these three pins controls the three output drivers, AHO, BHO and CHO. When

xHI is low, xHO is high. When xHI is high, xHO is low. DIS (Disable) overrides all input signals. xHI can be

driven by signal levels of 0V to 15V (no greater than VDD). If these pins are not driven, an internal 100µA

current source pulls them high.

5VSS

Chip ground.

UVLO

Undervoltage setting. A resistor can be connected between this pin and VSS to program the under voltage

set point - see Figure 7. With this pin not connected the undervoltage set point is typically 7V. When this

pin is tied to VDD, the undervoltage set point is typically 6.2V.

DIS

Disable input. Logic level input that when taken high sets all three outputs low. DIS high overrides all other

inputs. When DIS is taken low the outputs are controlled by the other inputs. DIS can be driven by signal

levels of 0V to 15V (no greater than VDD). An internal 100µA pull-up holds DIS high when this pin is not

driven.

AHO

BHO

CHO

(xHO)

Gate connections. Connect to the gates of the power MOSFETs in each phase.

AHS

BHS

CHS

(xHS)

MOSFET source connection. Connect the sources of the power MOSFETs and the negative side of the

bootstrap capacitors to these pins. In high side switch applications, 2mA of current will ﬂow out of these

pins into the load when the upper FETs are off. This current is necessary to guarantee that the upper FETs

stay off. This current tends to pull xHS high. For proper refresh, the load must pull the voltage on xHS down

to at least 7V below VDD. For example, when VDD = 12V, xHS must be pulled down to 5V. Therefore, the

minimum load necessary for proper refresh is given by the following equation: RMIN = 5V/2mA = 2.5kΩ. So

in this case, if the load has an impedance less than 5k

Ω, refresh will happen automatically at start up.

VDD

Positive supply rail. Bypass this pin to VSS with a capacitor >1µF. In applications where the bus voltage and

chip VDD are at the same potential, it is a good idea to run a separate line from the supply to each. This

greatly simpliﬁes the ﬁltering requirements.

HIP4083

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