ADE7758_15 datasheet(55/72 Pages) AD

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Data Sheet

ADE7758

Rev. E | Page 55 of 72

Step 1: Set configuration registers for zero crossings on all

phases by writing the value 0x38 to the LCYCMODE register

(0x17). This sets all of the ZXSEL bits to Logic 1.

Step 2: Set the interrupt mask register for zero-crossing

detection on all phases by writing 0xE00 to the MASK[0:24]

Step 3: Set up the calibration system for one of the two test

conditions: ITEST and VNOM, and IFULLSCALE/500 and VFULLSCALE/20.

Step 4: Read the rms registers after the zero-crossing interrupt

and take an average of N samples. This is recommended to get

the most stable rms readings. This procedure is detailed in

Figure 85: Steps 4a through 4e.

Step 4a. Choose the number of samples, N, to be averaged.

Step 4b. Reset the interrupt status register by reading RSTATUS

(0x1A).

Step 4c. Wait for the zero-crossing interrupt. When the zero-

crossing interrupt occurs, move to Step 4d.

Step 4d. Read the xIRMS and xVRMS registers. These values

will be averaged in Step 4e.

Step 4e: Average the N samples of xIRMS and xVRMS. The

averaged values will be used in Step 5.

Step 5: Write to the xVRMSOS (0x33 to 0x35) and xIRMSOS

(0x36 to 0x38) registers according to the following equations:

() (

)

16384

TEST

MIN

ITEST

MIN

IMIN

TEST

–

IRMS

–

IRMS

xIRMSOS

(77)

where:

IMIN is the full scale current/500.

ITEST is the test current.

IRMSIMIN and IRMSITEST are the current rms register values

without offset correction for the inputs IMIN and ITEST,

respectively.

NOM

MIN

VNOM

MIN

VMIN

NOM

–

VRMS

–

VRMS

xVRMSOS

(78)

where:

VMIN is the full scale voltage/20

VNOM is the nominal line voltage.

VRMSVMIN and VRMSVNOM are the voltage rms register values

without offset correction for the input VMIN and VNOM,

respectively.

Example: Calibration of RMS Offsets

For this example, ITEST = 10 A, IMAX = 100 A, VNOM = 220 V,

VFULLSCALE = 500 V, Power Factor = 1, and Frequency = 50 Hz.

Twenty readings are taken synchronous to the zero crossings of

all three phases at each current and voltage to determine the

average xIRMS and xVRMS readings. At ITEST and VNOM, the

example ADE7758 meter gets an average AIRMS (0x0A)

reading of 148242.2 and 744570.8 in the AVRMS (0x0D)

260 mA. At IMIN, the average AIRMS reading is 3885.68. At

VMIN = VFULLSCALE/20 or 25 V, the example meter gets an average

AVRMS of 86362.36. Using this data, −15d is written to

AIRMSOS (0x36) and −31d is written to AVRMSOS (0x33)

registers according to the Equation 77 and Equation 78.

() (

()

)

0xFF2

–

260

148242.2

260

–

3885.68

16384

−

AIRMSOS

() (

)

()

0xFE1

220

–

744570.8

–

86362.36

220

−

AVRMSOS

This example shows the calculations and measurements for

Phase A only. However, all three xIRMS and xVRMS registers

can be read simultaneously to compute the values for each

xIRMSOS and xVRMSOS register.

CHECKSUM REGISTER

The ADE7758 has a checksum register CHKSUM[7:0] (0x7E)

to ensure the data bits received in the last serial read operation

are not corrupted. The 8-bit checksum register is reset before

the first bit (MSB of the register to be read) is put on the DOUT

pin. During a serial read operation, when each data bit becomes

available on the rising edge of SCLK, the bit is added to the

checksum register. In the end of the serial read operation, the

contents of the checksum register are equal to the sum of all the

1s in the register previously read. Using the checksum register, the

user can determine if an error has occurred during the last read

operation. Note that a read to the checksum register also

generates a checksum of the checksum register itself.

DOUT

ADDR: 0x7E

CHECKSUM

CONTENT OF REGISTERS

(N-BYTES)

Figure 86. Checksum Register for Serial Interface Read

INTERRUPTS

The ADE7758 interrupts are managed through the interrupt

status register (STATUS[23:0], Address 0x19) and the interrupt

mask register (MASK[23:0], Address 0x18). When an interrupt

event occurs in the ADE7758, the corresponding flag in the

interrupt status register is set to a Logic 1 (see Table 24). If the

mask bit for this interrupt in the interrupt mask register is

Logic 1, then the IRQ logic output goes active low. The flag bits

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