ADE7166_15 datasheet(142/152 Pages) AD

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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Rev. B | Page 142 of 1

I/O PORTS

PARALLEL I/O

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/

ADE7569 use three input/output ports to exchange data with

external devices. In addition to performing general-purpose

I/O, some are capable of driving an LCD or performing alternate

functions for the peripherals available on-chip. In general, when

a peripheral is enabled, the pins associated with it cannot be

used as a general-purpose I/O. The I/O port can be configured

through the SFRs listed in Table 155.

Table 155. I/O Port SFRs

SFR

Address

Bit Addressable

Description

0x80

Yes

Port 0 register.

0x90

Yes

Port 1 register.

0xA0

Yes

Port 2 register.

EPCFG

0x9F

Extended port

configuration.

PINMAP0

0xB2

Port 0 weak

pull-up enable.

PINMAP1

0xB3

Port 1 weak

pull-up enable.

PINMAP2

0xB4

Port 2 weak

pull-up enable.

The three bidirectional I/O ports have internal pull-ups that can

be enabled or disabled individually for each pin. The internal

pull-ups are enabled by default. Disabling an internal pull-up

causes a pin to become open drain. Weak internal pull-ups are

configured through the PINMAPx SFRs.

Figure 116 shows a typical bit latch and I/O buffer for an I/O

pin. The bit latch (one bit in the SFR of each port) is represented

as a Type D flip-flop, which clocks in a value from the internal

bus in response to a write-to-latch signal from the CPU. The

Q output of the flip-flop is placed on the internal bus in response

to a read latch signal from the CPU. The level of the port pin

itself is placed on the internal bus in response to a read pin

signal from the CPU. Some instructions that read a port activate

the read latch signal, and others activate the read pin signal. See

the Read-Modify-Write Instructions section for details.

READ

LATCH

INTERNAL

BUS

WRITE

TO LATCH

READ

LATCH

DVDD

Px.x

INTERNAL

PULL-UP

ALTERNATE

OUTPUT

FUNCTION

ALTERNATE

INPUT

FUNCTION

CLOSED: PINMAPx.x = 0

OPEN: PINMAPx.x = 1

Figure 116. Port 0 Bit Latch and I/O Buffer

Weak Internal Pull-Ups Enabled

A pin with weak internal pull-up enabled is used as an input by

writing a 1 to the pin. The pin is pulled high by the internal pull-

ups, and the pin is read using the circuitry shown in Figure 116.

If the pin is driven low externally, it sources current because of

the internal pull-ups.

A pin with internal pull-up enabled is used as an output by

writing a 1 or a 0 to the pin to control the level of the output. If

a 0 is written to the pin, it drives a logic low output voltage

(VOL) and is capable of sinking 1.6 mA.

Open Drain (Weak Internal Pull-Ups Disabled)

When the weak internal pull-up on a pin is disabled, the pin

becomes open drain. Use this open-drain pin as a high impedance

input by writing a 1 to the pin. The pin is read using the circuitry

shown in Figure 116. The open-drain option is preferable for

inputs because it draws less current than the internal pull-ups

that were enabled.

38 kHz Modulation

Every ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/

ADE7569 provides a 38 kHz modulation signal. The 38 kHz

modulation is accomplished by internally XOR’ing the level

written to the I/O pin with a 38 kHz square wave. Then, when

a 0 is written to the I/O pin, it is modulated as shown in

Figure 117.

38kHz MODULATION

SIGNAL

OUTPUT AT

MOD38 PIN

LEVEL WRITTEN

TO MOD38

Figure 117. 38 kHz Modulation

Uses for this 38 kHz modulation include IR modulation of

a UART transmit signal or a low power signal to drive an

LED. The modulation can be enabled or disabled with the

MOD38EN bit (Bit 4) in the CFG SFR (Address 0xAF). The

38 kHz modulation is available on eight pins, selected by the

MOD38[7:0] bits in the extended port configuration SFR

(EPCFG, Address 0x9F).

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