REV. A

AD8302

–21–

Table III. Evaluation Board Configuration Options

Component

Function

Default Condition

P1

Power Supply and Ground Connector: Pin 2 VPOS and Pins 1 and 3 Ground.

Not Applicable

R1, R2

Input Termination. Provide termination for input sources.

R1 = R2 = 52.3

Ω (Size 0402)

R3

VREF Output Load. This load is optional and is meant to allow the user to simulate

R3 = 1 k

Ω (Size 0603)

their circuit loading of the device.

R5, R6, R9

Snubbing Resistor

R5 = R6 = 0

Ω (Size 0603)

R9 = 0

Ω (Size 0603)

C3, C7, R4

Supply Decoupling

C3 = 100 pF (Size 0603)

C7 = 0.1

µF (Size 0603)

R4 = 0

Ω (Size 0603)

C1, C5

Input AC-Coupling Capacitors

C1 = C5 = 1 nF (Size 0603)

C2, C8

Video Filtering. C2 and C8 limit the video bandwidth of the gain and phase

C2 = C8 = Open (Size 0603)

output respectively.

C4, C6

Offset Feedback. These set the high-pass corner of the offset cancellation loop

and thus with the input ac-coupling capacitors the minimum operating frequency.

C4 = C6 = 1 nF (Size 0603)

SW1

GSET Signal Source. When SW1 is in the position shown, the device is in gain

SW1 = Installed

measure mode; when switched, it operates in comparator mode and a signal

must be applied to GSET.

SW2

PSET Signal Source. When SW2 is in the position shown, the device is in phase

SW1 = Installed

measure mode; when switched, it operates in comparator mode and a signal

must be applied to PSET.

Figure 15a. Component Side Metal of Evaluation Board

Figure 15b. Component Side Silkscreen of Evaluation Board

Table II. P1 Pin Allocations

1

Common

2

VPOS

3

Common

R5

GAIN

SW1

GSET

VREF

PSET

PHASE

R9

R3

R6

SW2

AD8302

C2

C8

R7

R8

C7

VP

VP

1

COMM

INPA

2

OFSA

3

VPOS

4

OFSB

5

INPB

6

COMM

7

C1

C4

C6

C5

R4

C3

INPA

INPB

R1

R2

GND

Figure 14. Evaluation Board Schematic