5-51

(See Figure 3)

PARAMETER

(V)

LIMITS

UNITS

CDP1854A

CDP1854AC

(NOTE 1)

TYP

(NOTE 2)

MAX

(NOTE 1)

TYP

(NOTE 2)

MAX

TRANSMITTER TIMING - MODE 1

Minimum Clock Period

5

250

310

250

310

ns

10

125

155

-

-

ns

Minimum Pulse Width

Clock Low Level

5

100

125

100

125

ns

10

75

100

-

-

ns

Clock High Level

5

100

125

100

125

ns

10

75

100

-

-

ns

TPB

5

100

150

100

150

ns

10

50

75

-

-

ns

Minimum Setup Time

TPB to Clock

5

175

225

175

225

ns

10

90

150

-

-

ns

Propagation Delay Time

Clock to Data Start Bit

5

300

450

300

450

ns

10

150

225

-

-

ns

TPB to THRE

5

200

300

200

300

ns

10

100

150

-

-

ns

Clock to THRE

5

200

300

200

300

ns

10

100

150

-

-

ns

NOTES:

2. Maximum limits of minimum characteristics are the values above which all devices function.

NOTES:

1. The holding register is loaded on the trailing edge of TPB.

3. Write is the overlap of TPB, CS1, and CS3 = 1 and CS3, RD/WR = 0.

FIGURE 3. TRANSMITTER TIMING DIAGRAM - MODE 1

T CLOCK

THRE

WRITE (TPB)

SDO

12

1ST DATA BIT

TRANSMITTER SHIFT

REGISTER LOADED

(NOTE 2)

TRANSMITTER HOLDING

REGISTER LOADED

(NOTE 1)

34

56

7

14

15

16

1

23

4

(NOTE 3)

CDP1854A, CDP1854AC