4-78

Logic Diagrams

FIGURE 1. EQUIVALENT LOGIC DIAGRAM (1 OF 8 LATCHES

SHOWN) FOR CDP1872C

FIGURE 2. EQUIVALENT LOGIC DIAGRAM (1 OF 8 LATCHES

SHOWN) for CDP1874C

FIGURE 3. EQUIVALENT LOGIC DIAGRAM (1 OF 8 LATCHES SHOWN) FOR CDP1875C

PARAMETER

LIMITS

UNITS

CDP1872C, CDP1874C

MIN

(NOTE 1)

TYP

(NOTE 2)

MAX

INPUT PORT (FIGURE 4)

Output Enable

-45

90

ns

Output Disable

-45

90

ns

Clock to Data Out

-45

90

ns

Clear to Output

-

80

160

ns

Data In to Data Out

-50

85

ns

Minimum Data Setup Time

-10

30

ns

Data Hold Time

-10

30

ns

Minimum Clock Pulse Width

-30

60

ns

Minimum Clear Pulse Width

-30

60

ns

NOTES:

D

C

R

Q

CS1

CS2

DI

CLOCK

CLR

DO

D

C

R

Q

CS1

CS2

DI

CLOCK

CLR

DO

D

C

R

Q

CS1

CS3

CLR

DO

CS2

DI

CDP1872C, CDP1874C, CDP1875C