6-24

Features

• Fast Access Time

• Common Data Inputs and Outputs

• Multiple Chip Select Inputs to Simplify Memory

System Expansion

Description

The CDP1823 and CDP1823C are 128-word by 8-bit CMOS

SOS static random-access memories. These memories are

compatible with general-purpose microprocessors. The two

memories are functionally identical. They differ in that the

CDP1823 has a recommended operating voltage range of

4V to 10.5V, and the CDP1823C has a recommended oper-

ating voltage range of 4V to 6.5V.

The CDP1823 memory has 8 common data input and data

output terminals for direct connection to a bidirectional data

bus and is operated from a single voltage supply. Five chip-

select inputs are provided to simplify memory-system expan-

sion. In order to enable the CDP1823, the chip-select inputs

CS2, CS3 and CS5 require a low input signal, and the chip-

select inputs CS1 and CS4 require a high input signal.

The MRD signal enables all 8 output drivers when in the low

state and should be in a high state during a write cycle.

After valid data appear at the output, the address inputs may

be changed immediately. Output data will be valid until either

(access time) after address changes.

Pinout

Ordering Information

5V

10V

PACKAGE

TEMP. RANGE

PKG.

NO.

CDP1823CE

CDP1823E

PDIP

CDP1823CD

CDP1823D

SBDIP

CDP1823CDX

-

Burn-In

D24.6

CDP1823, CDP1823C

(PDIP, SBDIP)

TOP VIEW

1

2

3

4

5

6

7

8

9

10

11

12

BUS 0

BUS 1

BUS 2

BUS 3

BUS 4

BUS 5

BUS 6

BUS 7

CS1

CS2

CS3

16

17

18

19

20

21

22

23

24

15

14

13

MA1

MA2

MA3

MA4

MA6

MRD

CS5

CS4

MA0

MA5

MWR

March 1997

CDP1823,

CDP1823C

128-Word x 8-Bit

LSI Static RAM

File Number

1198.2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207