7-985

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

CD4068BMS

CMOS 8 Input NAND/AND Gate

Pinout

CD4068BMS

TOP VIEW

Functional Diagram

K = A · B · C · D · E · F · G · H

A

B

C

D

NC

VSS

VDD

J = A · B · C · D · E · F · G · H

H

G

F

E

NC

1

2

3

4

5

6

7

14

13

12

11

10

9

8

NC = NO CONNECTION

12

11

10

9

2

3

4

5

A

B

C

D

E

F

G

H

13

J

K

1

J = A · B · C · D · E · F · G · H

K = A · B · C · D · E · F · G · H

VDD = 14

VSS = 7

6, 8 = NO CONNECTION

Features

• High Voltage Type (20V Rating)

• Medium Speed Operation

- TPHL, TPLH = 75ns (Typ.) at VDD = 10V

• Buffered Inputs and Outputs

• 5V, 10V and 15V Parametric Ratings

• Standardized Symmetrical Output Characteristics

• 100% Tested for Quiescent Current at 20V

• Maximum Input Current of 1

µA at 18V Over Full Pack-

• Noise Margin (Over Full Package/Temperature Range)

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Specifications for Description of

‘B’ Series CMOS Devices”

Description

CD4068BMS NAND/AND gate provides the system designer

with direct implementation of the positive logic 8 Input NAND and

AND functions and supplements the existing family of CMOS

gates.

The CD4068BMS is supplied in these 14 lead outline packages:

Braze Seal DIP

H4H

Frit Seal DIP

H1B

Ceramic Flatpack

H3W

December 1992

Logic Diagram

FIGURE 1. LOGIC DIAGRAM

13 J

1

K

2

A

3

B

4

C

5

D

9

E

10

F

11

G

12

H

File Number

3320