7-67

Specifications CD4013BMS

Logic Diagram

FIGURE 1. ONE OF TWO IDENTICAL FLIP-FLOPS

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

FUNCTION

OPEN

GROUND

VDD

9V

± -0.5V

OSCILLATOR

50kHz

25kHz

Static Burn-In 1

(Note 1)

1, 2, 12, 13

3-11

14

Static Burn-In 2

(Note 1)

1, 2, 12, 13

7

3-6, 8-11, 14

Dynamic Burn-

In (Note 1)

-

4, 6-8, 10

14

1, 2, 12, 13

3, 11

5, 9

Irradiation

(Note 2)

1, 2, 12, 13

7

3-6, 8-11, 14

NOTE:

1. Each pin except VDD and GND will have a series resistor of 10K

± 5%, VDD = 18V ± 0.5V

2. Each pin except VDD and GND will have a series resistor of 47K

± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,

VDD = 10V

± 0.5V

TRUTH TABLE

CL*

DR

SQ

Q

00001

No

Change

10010

X0

0

Q

Q

X

X

1001

X

X

0110

X

X

1111

Logic 0 = Low

Logic 1 = High

* = Level change

X = Don’t care

N(N) = FF1/FF2 terminal assignments

p

n

TG

CL

CL

p

n

TG

CL

CL

p

n

TG

CL

CL

p

n

TG

CL

CL

* All inputs are protected by CMOS protection network

RESET

DATA

SET

CL

CL

CL

VDD

VSS

14

7

MASTER SECTION

SLAVE SECTION

BUFFERED OUTPUTS

2(12)

Q

1(13)

Q