ST78C36/36A

9

REV. 5.1.0

ECP/EPP PARALLEL PRINTER PORT WITH 16-BYTE FIFO

Cnfg-B Bits 5-3:

Select an IRQ channel per the following table:

000

001

7

001

001

7 (Default)

010

010

9

011

001

7

100

001

7

101

001

7

110

001

7

111

111

5

Cnfg-B Bit-6:

Returns the true value of the selected IRQ pad.

Cnfg-B Bit-7:

Indicates RLE compression is not supported.

3.12

EXTENDED CONTROL REGISTER ( ECR )

The Extended Control Register has a system RESET state of 10010101. The significance of the bits is defined

by the ECP specification as:

ECR Bit-0:

This read-only bit returns FIFO empty status (FIFO-E) and is forced high unless PPF, ECP, or TST mode is

selected.

0 = At least one byte of data contains in the FIFO.

1 = FIFO is empty.

ECR Bit-1:

This read-only bit returns FIFO full status (FIFO-F) and is forced low unless PPF, ECP, or TST mode is

selected.

0 = At least one empty location is available in the FIFO.

1 = FIFO is full.

IRQ