1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207

ACTS20MS

Radiation Hardened

Dual 4-Input NAND Gate

Pinouts

14 LEAD CERAMIC DUAL-IN-LINE

MIL-STD-1835 DESIGNATOR, CDIP2-T14, LEAD FINISH C

TOP VIEW

14 LEAD CERAMIC FLATPACK

MIL-STD-1835 DESIGNATOR, CDFP3-F14, LEAD FINISH C

TOP VIEW

A1

B1

NC

C1

D1

Y1

GND

VCC

D2

C2

NC

B2

A2

Y2

1

2

3

4

5

6

7

14

13

12

11

10

9

8

14

13

12

11

10

9

8

2

3

4

5

6

7

1

A1

B1

NC

C1

D1

Y1

GND

VCC

D2

C2

NC

B2

A2

Y2

April 1995

Truth Table

INPUTS

OUTPUT

An

Bn

Cn

Dn

Yn

L

XXX

H

XLX

X

H

XX

L

X

H

XXX

L

H

HHHH

L

NOTE: L = Logic Level Low, H = Logic level High, X = Don’t Care

Functional Diagram

An

Bn

Yn

Cn

Dn

(5, 13)

(4, 12)

(2, 10)

(1, 9)

(6, 8)

Features

• 1.25 Micron Radiation Hardened SOS CMOS

• Total Dose 300K RAD (Si)

• Single Event Upset (SEU) Immunity

• Latch-Up Free Under Any Conditions

• Significant Power Reduction Compared to ALSTTL Logic

• DC Operating Voltage Range: 4.5V to 5.5V

• Input Logic Levels

- VIL = 0.8V Max

- VIH = VCC/2V Min

• Input Current

≤1µA at VOL, VOH

Description

The Intersil ACTS20MS is a radiation hardened dual 4-input

NAND gate. A low on any input forces the output to a high logic

state.

The ACTS20MS utilizes advanced CMOS/SOS technology to

achieve high-speed operation. This device is a member of the

radiation hardened, high-speed, CMOS/SOS Logic Family.

Ordering Information

PART NUMBER

TEMPERATURE RANGE

SCREENING LEVEL

PACKAGE

ACTS20DMSR

Intersil Class S Equivalent

14 Lead SBDIP

ACTS20KMSR

Intersil Class S Equivalent

14 Lead Ceramic Flatpack

ACTS20D/Sample

Sample

14 Lead SBDIP

ACTS20K/Sample

Sample

14 Lead Ceramic Flatpack

ACTS20HMSR

Die

Die

Spec Number

518824

File Number

3611