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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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ACTS10MS

Radiation Hardened

Triple Three-Input NAND Gate

Pinouts

14 LEAD CERAMIC DUAL-IN-LINE

MIL-STD-1835 DESIGNATOR CDIP2-T14, LEAD FINISH C

TOP VIEW

14 LEAD CERAMIC FLATPACK

MIL-STD-1835 DESIGNATOR CDFP3-F14, LEAD FINISH C

TOP VIEW

A1

B1

A2

B2

C2

Y2

GND

VCC

C1

Y1

C3

B3

A3

Y3

1

2

3

4

5

6

7

14

13

12

11

10

9

8

14

13

12

11

10

9

8

2

3

4

5

6

7

1

A1

B1

A2

B2

C2

Y2

GND

VCC

C1

Y1

C3

B3

A3

Y3

Features

• 1.25 Micron Radiation Hardened SOS CMOS

• Total Dose 300K RAD (Si)

• Single Event Upset (SEU) Immunity

• Latch-Up Free Under Any Conditions

• Significant Power Reduction Compared to ALSTTL Logic

• DC Operating Voltage Range: 4.5V to 5.5V

• Input Logic Levels

- VIL = 0.8V Max

- VIH = VCC/2V Min

• Input Current

≤1µA at VOL, VOH

Description

The Intersil ACTS10MS is a radiation hardened triple three-input

NAND gate. A high on all inputs forces the output to a low state.

The ACTS10MS utilizes advanced CMOS/SOS technology to

achieve high-speed operation. This device is a member of the

radiation hardened, high-speed, CMOS/SOS Logic Family.

April 1995

Ordering Information

PART NUMBER

TEMPERATURE RANGE

SCREENING LEVEL

PACKAGE

ACTS10DMSR

Intersil Class S Equivalent

14 Lead SBDIP

ACTS10KMSR

Intersil Class S Equivalent

14 Lead Ceramic Flatpack

ACTS10D/Sample

Sample

14 Lead SBDIP

ACTS10K/Sample

Sample

14 Lead Ceramic Flatpack

ACTS10HMSR

Die

Die

Truth Table

INPUTS

OUTPUT

An

Bn

Cn

Yn

LLL

H

LL

H

H

LHL

H

LH

H

H

HL

L

H

HLH

H

HH

L

H

HHH

L

NOTE: L = Logic Level Low, H = Logic Level High

Functional Diagram

An

Bn

Yn

(12, 6, 8)

(1, 3, 9)

(2, 4, 10)

(5, 11, 13)

Cn

Spec Number

518823

File Number

3631