87C196 datasheet(21/25 Pages) INTEL

21 / 25 page

87C196KRKQ 87C196JVJT 87C196JRJQ

52-LEAD DEVICES

Intel offers 52-lead versions of the 87C196KR de-

vice the 87C196JVJTJRJQ devices The first

samples and production units use the 87C196KR die

and bond it out in a 52-lead package

It is important to point out some functionality differ-

ences because of future devices or to remain soft-

ware consistent with the 68-lead device Because of

the absence of pins on the 52-lead device some

functions are not supported

52-Lead Unsupported Functions

Analog Channels 0 and 1

INST Pin Functionality

SLPINT Pin Support

HLD HLDA Functionality

External ClockingDirection of Timer1

WRH or BHE Functions

Dynamic Buswidth

Dynamic Wait State Control

The following is a list of recommended practices

when using the 52-lead device

(1) External Memory Use an 8-bit bus mode only

There is neither a WRH or BUSWIDTH pin The

bus cannot dynamically switch from 8- to 16-bit

or vice versa Set the CCB bytes to an 8-bit only

mode using WR function only

(2) Wait State Control Use the CCB bytes to con-

figure the maximum number of wait states If the

READY pin is selected to be a system function

the device will lockup waiting for READY If the

READY pin is configured as LSIO (default after

RESET) the internal logic will receive a logic

‘‘0’’ level and insert the CCB defined number of

wait states in the bus cycle DON’T USE IRC e

‘‘111’’

(3) NMI Support The NMI is not bonded out Make

the NMI vector at location 203Eh vector to a

Return instruction This is for glitch safety pro-

tection only

(4) Auto-Programming Mode The 52-lead device

will ONLY support the 16-bit zero wait state bus

during auto-programming

(5) EPA4 through EPA7 Since the JR and JQ de-

vices use the KR silicon these functions are in

the device just not bonded out A programmer

can use these as compare only channels or for

other functions like software timer start an AD

conversion or reset timers

(6) Slave Port Support The Slave port cannot be

easily

used

52-lead

devices

due

P54SLPINT and P51SLPCS not being bond-

ed-out

(7) Port Functions Some port pins have been re-

moved P57 P56 P55 P51 P62 P63 P14

through P17 P23 P25 P00 and P01 The

PxREG PxSSEL and PxIO registers can still be

updated and read The programmer should not

use the corresponding bits associated with the

removed port pins to conditionally branch in

software Treat these bits as RESERVED

Additionally these port pins should be setup in-

ternally by software as follows

1 Written to PxREG as ‘‘1’’ or ‘‘0’’

2 Configured as PushPull PxIO as ‘‘0’’

3 Configured as LSIO

This configuration will effectively strap the pin

either high or low

DO NOT Configure as

Open Drain output ‘’1’’ or as an Input pin

This device is CMOS

87C196KRKQJVJTJRJQ ERRATA

1 VOH2 IOH2 Specification (Note C)

In the DC Characteristics section of this data-

sheet VOH2 indicates the strength of the internal

weak pullups that are active during and after re-

set until the user writes to the PxMODE register

C-step devices do not meet this specification

The new specification for C-step devices is VOH2

(min) e VCC b 1V at IOH2 eb6 mA Note that

JRJQ D-step devices are not affected by this

errata and meet the published specification

2 1B00h – 1BDFh External Addressing

(Notes C D)

Affected devices cannot access external memory

locations 1B00h – 1BDFh A bus cycle does not

occur when these addresses are accessed If at-

tempting to read from 1B00h – 1BDFh a value of

FFh is returned even though a read cycle is not

generated Writing to these locations will not gen-

erate an external bus cycle either This errata has

been corrected on JV and JT devices

3 Port3 Push-Pull Operation (Note C)

If Port3 is operating as a push-pull LSIO (Low-

Speed IO) port and an addressdata bus cycle

occurs Port3 will continue to drive the address

data bus with its LSIO data during the bus cycle

It is rather unlikely that this errata would affect an

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