87C196KT87C196KS

Device

PinsPackage

EPROM

Reg RAM

Code RAM

IO

EPA

SIO

SSIO

AD

87C196KT

68-Pin PLCC

32K

1K

512b

56

10

Y

Y

8

87C196KS

68-Pin PLCC

24K

1K

256b

56

10

Y

Y

8

NOTE

This is a PRODUCT PREVIEW DATA SHEET The AC and DC parameters contained within this data sheet may change

after full automotive temperature characterization of the device has been performed Contact your local sales office before

finalizing the Timing and DC characteristics of a design to verify you have the latest information

ARCHITECTURE

The KTKS are new members of the MCS-96 family

having the same architecture and use the same in-

struction set as the 80C196KB Many new features

have been added including

CPU FEATURES

Y

Powerdown and Idle Modes

Y

16 MHz Operating Frequency

Y

A High Performance Peripheral

Transaction Server (PTS)

Y

37 Interrupt Vectors

Y

Up to 512 Bytes of Additional Code

RAM

Y

Up to 1 Kbyte of Additional Register

RAM

Y

‘‘Windowing’’ Allows 8-Bit Addressing

to some 16-Bit Addresses

Y

175 ms 16 x 16 Multiply

Y

3 ms 3216 Divide

Y

Oscillator Fail Detect Circuitry

PERIPHERAL FEATURES

Programmable AD Conversion and SH Times

10 CaptureCompare IO with 2 Flexible Timers

(250 ns Resolution and Double Buffered Inputs)

Synchronous Serial IO Port for Full Duplex Seri-

al IO

SynchronousAsynchronous

Serial

IO

Port

(with Dedicated 16-Bit Baud Rate Generator)

Total Utilization of ALL Available Pins (IO Mux’d

with Control)

(2) 16-Bit Timers with Prescale Cascading and

Quadrature Counting Capabilities

Up to 12 Externally Triggered Interrupts

NEW INSTRUCTIONS

XCHXCHB Exchange the contents of two loca-

tions either Word or Byte is support-

ed

BMOVI

Interruptable Block Move Instruction

allows the user to be interrupted dur-

ing long executing Block Moves

TIJMP

Table Indirect JUMP This instruction

incorportes a way to do complex

CASE level branches through one in-

struction An example of such code

savings several interrupt sources and

only one interrupt vector The TIJMP

instruction will sort through the sourc-

es and branch to the appropriate sub-

code level in one instruction This in-

struction was added especially for the

EPA structure but has other code sav-

ing advantages

EPTSDPTS Enable and Disable Interrupts (Works

like EI and DI)

SFR OPERATION

A total of 1 Kbyte of Register RAM is implemented

on the 87C196KTKS devices These locations sup-

port the on-chip peripherals that the 87C196KTKS

has (SFR’s) as well as offering a data storage area

These locations are all 8-bit directly addressable by

use of the windowing technique Any 32- 64- or 128-

byte section can be relocated into the upper 32- 64-

or 128-byte area of the Register RAM area 080H –

0FFH

2

2