82C55 datasheet(2/23 Pages) INTEL

2 / 23 page

82C55A

Table 1 Pin Description

Symbol

Pin Number

Type

Name and Function

Dip

PLCC

PA3–0

1–4

2–5

I O

PORT A PINS 0 – 3

Lower nibble of an 8-bit data output latch

buffer and an 8-bit data input latch

READ CONTROL

This input is low during CPU read operations

CHIP SELECT

A low on this input enables the 82C55A to

respond to RD and WR signals RD and WR are ignored

otherwise

GND

System Ground

A1–0

8–9

9–10

ADDRESS

These input signals in conjunction RD and WR

control the selection of one of the three ports or the control

word registers

Input Operation (Read)

00010

Port A - Data Bus

01010

Port B - Data Bus

10010

Port C - Data Bus

11010

Control Word - Data Bus

Output Operation (Write)

00100

Data Bus - Port A

01100

Data Bus - Port B

10100

Data Bus - Port C

11100

Data Bus - Control

Disable Function

XXXX

Data Bus-3- State

PC7–4

10 – 13

1113 – 15

PORT C PINS 4 – 7

Upper nibble of an 8-bit data output latch

buffer and an 8-bit data input buffer (no latch for input) This port

can be divided into two 4-bit ports under the mode control Each

4-bit port contains a 4-bit latch and it can be used for the control

signal outputs and status signal inputs in conjunction with ports

A and B

PC0–3

14–17

16–19

I O

PORT C PINS 0 – 3

Lower nibble of Port C

PB0-7

18 – 25

20 – 22

PORT B PINS 0 – 7

An 8-bit data output latchbuffer and an 8-

24 – 28

bit data input buffer

VCC

SYSTEM POWER a

5V Power Supply

D7–0

27 – 34

30 – 33

DATA BUS

Bi-directional tri-state data bus lines connected to

35 – 38

system data bus

RESET

A high on this input clears the control register and all

ports are set to the input mode

WRITE CONTROL

This input is low during CPU write

operations

PA7–4

37–40

41–44

I O

PORT A PINS 4 – 7

Upper nibble of an 8-bit data output latch

buffer and an 8-bit data input latch

1 12

No Connect

23 34

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