e5500 Core

The P5020 is based on the 64-bit e5500 Power

seven-stage pipeline for low latency response to

unpredictable code execution paths, boosting its

single-threaded performance. Key features:

• Supports up to 2.0 GHz core frequencies

• Tightly-coupled low latency cache hierarchy:

32 KB I/D (L1), 512 KB L2 per core

• Up to 2 MB of shared platform cache (L3)

• 3.0 DMIPS/MHz per core

• Up to 64 GB of addressable memory space

• Hybrid 32-bit mode to support legacy software

and seamless transition to 64-bit architecture

Virtualization

The P5020 includes support for hardware-

assisted virtualization. The e5500 core offers

an extra core privilege level (hypervisor).

Virtualization software for the P5 family includes

containers, Freescale hypervisor and commercial

QorIQ Communications Platforms

QorIQ

P5020/P5010 Processors

Overview

The QorIQ P5 family delivers scalable 64-bit processing with single-, dual- and

quad-core devices. With frequencies scaling up to 2.0 GHz, a tightly coupled cache

hierarchy for low latency and integrated hardware acceleration, the P5020 (dual-core)

and P5010 (single-core) devices are ideally suited for compute intensive, power-

conscious control plane applications.

Target Markets and Applications

The P5020 is designed for high-

performance, power-constrained control

plane applications and provides an

ideal combination of core performance,

integrated accelerators and advanced I/O

required for the following compute-intensive

applications:

• Enterprise equipment: Router, switch,

services

• Data center: Server appliance, SAN

storage controller, iSCSI controller,

FCoE bridging

• Aerospace and defense

• Industrial computing: Single-board

computers, test/measurement, robotics

QorIQ P5020/P5010 Processors

Accelerators and Memory Control

Networking Elements

Core Complex (CPU, L2 and Frontside CoreNet Platform Cache)

Basic Peripherals and Interconnect

Real-Time Debug

10 GE

Parse, Classify,

Distribute

Security Fuse Processor

Security Monitor

2x USB 2.0

eSDHC

Queue

Mgr.

Buffer

Mgr.

Pattern

Match

Engine

2.0

Security

4.0

Frame Manager

Serial

Mgr.

RAID

5/6

Engine

1GE 1GE

1GE 1GE

1GE

eLBC

SD/MMC

2x DUART

SPI, GPIO

SRIO

PCIe/

SRIO

PCIe PCIe

RapidIO

Message

Unit

2x DMA

PCIe

Watchpoint

Cross

Trigger

Perf.

Monitor

CoreNet

Trace

Aurora

Peripheral Access

Management Unit

SATA

2.0

SATA

2.0

PAMU

PAMU

PAMU

PAMU

18-Lane 5 GHz SerDes

CoreNet Coherency Fabric

e5500 Core

512 KB

Backside

L2 Cache

32 KB

D-Cache

32 KB

I-Cache

1024 KB

Frontside CoreNet

Platform Cache

64-bit

DDR2/3

Memory Controller

1024 KB

Frontside CoreNet

Platform Cache

64-bit

DDR2/3

Memory Controller

*Only Available on P5020

*Only Available on P5020

QorIQ P5020/P5010 Processors

P5 Family Comparison Chart

P5020/P5010

P5040/P5021

CPU cores

2x 64-bit e5500, 1x (P5010)

4x 64-bit e5500, 2x (P5021)

Threads

2/1 (single thread per core)

4/2 (single thread per core)

Max core frequency 1.6 to 2.0 GHz

1.8 to 2.4 GHz

L2

512 KB per core

512 KB per core

L3/Platform

2 MB (P5020)/1 MB (P5010)

2 MB (both P5040 and P5021)

DDR I/F

2x 64-bit DDR3 (up to 1333 MT/s)

1x 64-bit DDR3 (P5010)

2x 64-bit DDR3 (up to 1600 MT/s)

4x PCIe v2.0

3x PCIe v2.0 (incl. 1 x 8)

GbE, 10 GbE

5x 1 GbE, 1x 10 GbE

10x 1 GbE, 2x 10 GbE

SRIO

2x SRIO v2.1

(supports Type 9 and 11 messaging)

N/A

SerDes lanes

18 lanes

20 lanes

Package

1295-pin 37.5 x 37.5 mm FC-PBGA

1295-pin 37.5 x 37.5 mm FC-PBGA