82527 datasheet(22/22 Pages) INTEL

22 / 22 page

82527

14 The timing diagrams for 8-Bit16-Bit Multiplexed

Intel Modes (Modes 01) have been changed to

show ALE rising before CS

falls

15 The following AC Characteristics for 8-Bit Mul-

tiplexed Non-Intel Modes (Modes 2) have been

changed

a 1tMCLK has been increased to 8 MHz from

5 MHz

b tSLAX has been decreased to 20 ns from

225 ns

c tEVDV has been decreased to (2 4) tMCLK a

100 ns from (2 4) tMCLK a 145 ns

d tELDV minimum has been decreased to

tMCLK from tMCLK a 100 ns

e tELDV maximum has been increased to

2tMCLK a 500 ns from 2 tMCLK a 100 ns

f tEHEL for registers except 02H 04H 05H

has been renamed to tELEL and the specifi-

cation has been decreased to 2 tMCLK a

145 ns from 4 tMCLK a 145 ns

g tSLEH has been increased to 20 ns from 0

h tCLSL has been added

i tELCH has been added

j The following definition was added for a

‘‘read cycle without a previous write’’ The

time between the falling edge of E (for the

previous write cycle) and the rising edge of

E (for the current read cycle) is greater than

2tMCLK

k The following definition was added for a

‘‘write cycle with a previous write’’ The time

between the falling edge of E (for the previ-

ous write cycle) and the next falling edge of

E (for the current write cycle) is less than

2tMCLK

16 The following AC Characteristics for 8-Bit Non-

Multiplexed Asynchronous Mode (Mode 3) have

been changed

a 1tMCLK has been increased to 8 MHz from

5 MHz

b tCLDV has been decreased for low speed

registers to (2 4) tMCLK a 100 ns from

(2 4) tMCLK a 145 ns

c tCHKH comment ‘‘with 33 KX Pullup and

100 pF Load’’ has been removed since

tCHKH is tested with a current source

d tCLKL for a Write Access with a Previous

Write has been renamed to tCHKL

e The note ‘‘E and AS must be tied high in this

mode’’ has been added

f The following definition was added for a

‘‘read cycle without a previous write’’ The

time between the rising edge of CS

(for

the previous write cycle) and the falling edge

of CS

(for the current read cycle) is great-

er than 2 tMCLK

g The following definition was added for a

‘‘write cycle with a previous write’’ The time

between the rising edge of CS

(for the pre-

vious write cycle) and the next rising edge of

(for the current write cycle) is less than

2tMCLK

17 The following AC Characteristics for 8-Bit Non-

Multiplexed Synchronous Mode (Mode 3) have

been changed

a 1tMCLK has been increased to 8 MHz from

5 MHz

b tELDZ minimum has been removed

c tAVCL has been added

d tCHAI has been added

e The following definition was added for a

‘‘read cycle without a previous write’’ The

time between the falling edge of E (for the

previous write cycle) and the rising edge of

E (for the current read cycle) is greater than

2tMCLK

f The following definition was added for a

‘‘write cycle with a previous write’’ The time

between the falling edge of E (for the previ-

ous write cycle) and the next falling edge of

E (for the current write cycle) is less than

2tMCLK

18 The following AC Characteristics for Serial In-

terface Mode have been changed

a tSKHI has been decreased to 84 ns from

119 ns

b tSKLO has been decreased to 84 ns from

119 ns

c tPDO has been decreased to 59 ns from

84 ns

d tSETUP has been decreased to 35 ns from

59 ns

e tHOLD has been decreased to 84 ns from

109 ns

19 The note in the AC Testing Input diagram refer-

enced VOH was previously named VIH

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