PIIX3 datasheet(78/122 Pages) INTEL

78 / 122 page

82371FB (PIIX) AND 82371SB (PIIX3)

2.6.2.

APMS—ADVANCED POWER MANAGEMENT STATUS PORT

I/O Address:

0B3h

Default Value:

00h

Attribute:

Read/Write

This register passes status information between the OS and the SMI handler. The PIIX/PIIX3 operation is not

effected by the data in this register.

Bit

Description

7:0

APM Status Port (APMS). Writes store data in this register and reads return the last data

written.

2.7.

PCI BUS Master IDE Registers

The PCI Bus master IDE function uses 16 bytes of I/O space, allocated via the BMIBA register (A PCI Base

Address register). All bus master IDE I/O space registers can be accessed as byte, word, or Dword

quantities. The description of the 16 bytes of I/O registers follows:

2.7.1.

BMICOM—BUS MASTER IDE COMMAND REGISTER

Address Offset:

Primary Channel—Base + 00h; Secondary Channel—Base + 08h

Default Value:

00h

Attribute:

Read / Write

This register enables/disables bus master capability for the IDE function and provides direction control for the

IDE DMA transfers. This register also provides bits that software uses to indicate DMA capability of the IDE

device.

Bit

Description

7:4

Reserved

Bus Master Read/Write Control (RWCON). 0=Reads; 1=Writes. This bit must NOT be

changed when the bus master function is active.

2:1

Reserved.

Start/Stop Bus Master (SSBM). 1=Start; 0=Stop. When this bit is set to 1, bus master

operation starts. The controller transfers data between the IDE device and memory only when

this bit is set. Master operation can be stopped by writing a 0 to this bit. This results in all state

information being lost (i.e., master mode operation cannot be stopped and then resumed).

If this bit is set to 0 while bus master operation is still active (i.e., Bit 0=1 in the Bus Master IDE

Status Register for that IDE channel) and the drive has not yet finished its data transfer (bit

2=0 in the channel's Bus Master IDE Status Register), the bus master command is aborted

and data transferred from the drive may be discarded before being written to system memory.

This bit is intended to be set to 0 after the data transfer is completed, as indicated by either bit

0 or bit 2 being set in the IDE Channel's Bus Master IDE Status Register.

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