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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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80960HA датащи(PDF) 72 Page - Intel Corporation |
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80960HA датащи(HTML) 72 Page - Intel Corporation |
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72 / 102 page  80960HA/HD/HT 66 Advance Information Datasheet The processor can stall (BSTALL asserted) even with an empty bus queue (BREQ deasserted). Depending on the instruction stream and memory wait states, the two signals can be separated by several CLKIN cycles. Bus arbitration logic that logically “ANDs” BSTALL and BREQ will not correctly grant the bus to the processor in all stall cases, potentially degrading processor performance. Do not logically “AND” BSTALL and BREQ together in arbitration logic. Instead, the simplest bus arbitration should logically “OR” BSTALL and BREQ to determine the processor’s bus ownership requirements. More sophisticated arbitration should recognize the priority nature of these two signals. Using a traffic light analogy, BREQ is a “yellow light” warning of a possible processor stall and BSTALL is a “red light” indicating a stall in progress. Figure 49. BREQ and BSTALL Operation CLKIN ADS BLAST BREQ BSTALL |
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