80960CF-30 datasheet(13/62 Pages) INTEL

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SPECIAL ENVIRONMENT 80960CF-30 -25 -16

Table 4 80960CF Pin DescriptionDMA and Interrupt Unit Control Signals

Name

Type

Description

DREQ3

DMA REQUEST

causes a DMA transfer to be requested Each of the four signals

request a transfer on a single channel DREQ0 requests channel 0 DREQ1 requests

DREQ2

A(L)

channel 1 etc When two or more channels are requested simultaneously the

DREQ1

H(Z)

channel with the highest priority is serviced first Channel priority mode is

DREQ0

R(Z)

programmable

DACK3

DMA ACKNOWLEDGE

indicates that a DMA transfer is being executed Each of the

four signals acknowledge a transfer for a single channel DACK0 acknowledges

DACK2

channel 0 DACK1 acknowledges channel 1 etc DACK30 are asserted when the

DACK1

H(1)

requesting device of a DMA is accessed

DACK0

R(1)

EOP3TC3

END OF PROCESSTERMINAL COUNT

can be programmed as either an input

(EOP30) or as an output (TC30) but not both Each pin is individually

EOP2TC2

A(L)

programmable When programmed as an input EOPx causes the termination of a

EOP1TC1

H(ZQ)

current DMA transfer for the channel corresponding to the EOPx pin EOP0

EOP0TC0

R(Z)

corresponds to channel 0 EOP1 corresponds to channel 1 etc When a channel is

configured for source

and destination chaining the EOP pin for that channel causes

termination of only the current buffer transferred and causes the next buffer to be

transferred EOP30 are asynchronous inputs

When programmed as an output the channel’s TCx pin indicates that the channel

byte count has reached 0 and a DMA has terminated TCx is driven with the same

timing as DACKx during the last DMA transfer for a buffer If the last bus request is

executed as multiple bus accesses TCx remains asserted for the entire bus request

XINT7

EXTERNAL INTERRUPT PINS

cause interrupts to be requested These pins can be

configured in three modes

XINT6

A(EL)

In Dedicated Mode each pin is a dedicated external interrupt source Dedicated

XINT5

H(Z)

inputs can be individually programmed to be level (low) or edge (falling) activated

XINT4

R(Z)

In Expanded Mode the 8 pins act together as an 8-bit vectored interrupt source The

XINT3

interrupt pins in this mode are level activated Since the interrupt pins are active low

XINT2

the vector number requested is the one’s complement of the positive logic value

XINT1

place on the port This eliminates glue logic to interface to combinational priority

XINT0

encoders which output negative logic

In Mixed Mode XINT75 are dedicated sources and XINT40 act as the 5 most

significant bits of an expanded mode vector The least significant bits are set to 010

internally

NMI

NON-MASKABLE INTERRUPT

causes a non-maskable interrupt event to occur

NMI is the highest priority interrupt recognized NMI is an edge (falling) activated

A(E)

source

H(Z)

R(Z)

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