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IDT7132LA55CI датащи(PDF) 12 Page - Integrated Device Technology |
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IDT7132LA55CI датащи(HTML) 12 Page - Integrated Device Technology |
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12 / 16 page ![]() 12 IDT7132SA/LA and IDT 7142SA/LA High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Write with BUSY(4) NOTES: 1. tWH must be met for both BUSY Input (IDT7142, slave) or Output (IDT7132, master). 2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH. 3. tWB applies only to the slave version (IDT7142). 4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A". Timing Waveform of Write with Port-to-Port Read and BUSY(2,3,4) BUSY"B" 2692 drw 12 R/ W"A" tWP tWH (1) tWB R/ W"B" (2) (3) , tWC tWP tDW tDH tBDD tDDD tBDA tWDD ADDR"B" DATAOUT"B" DATAIN"A" ADDR"A" MATCH VALID MATCH VALID R/ W"A" BUSY"B" tAPS (1) 2692 drw 11 tBAA NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for Slave (IDT7142). 2. CEL = CER = VIL 3. OE = VIL for the reading port. 4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A". |
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