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IDT71342LA55PF датащи(PDF) 6 Page - Integrated Device Technology

номер детали IDT71342LA55PF
подробное описание детали  HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE
PDF  13 Pages
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производитель  IDT [Integrated Device Technology]
домашняя страница  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT71342LA55PF датащи(HTML) 6 Page - Integrated Device Technology

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IDT71342SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE
COMMERCIAL TEMPERATURE RANGE
6.05
6
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE(1, 2, 4, 6)
NOTES:
1. Write cycle parameters should be adhered to, in order to ensure proper writing.
2.
CEL = CER = VIL. CE"B" = VIL.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
tAA or tSAA
ADDRESS
DATAOUT
PREVIOUS DATA VALID
DATA VALID
tOH
tOH
tRC
2721 drw 07
2721 drw 08
CE or SEM
DATAOUT
VALID DATA
tPD
tAOE
tACE
OE
tHZ
tLZ
tLZ
tPU
50%
50%
ICC
ISB
CURRENT
tHZ
tSOP
(5)
tSOP
(1)
(1)
(4)
(2)
(2)
(4)
2721 drw 09
R/
W "A"
VALID
tWC
MATCH
VALID
MATCH
tWP
tDW
tWDD
tDDD
ADDR "A"
DATAIN "A"
DATAOUT "B"
ADDR "B"
(1)
tDH
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE(1, 3)
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ (1, 2)
NOTES:
1. Timing depends on which signal is asserted last,
OE or CE.
2. Timing depends on which signal is de-asserted first,
OE or CE.
3. R/
W = VIH and address is valid prior to or coincident with CE transition Low.
4. Start of valid data depends on which timing becomes effective last; tAOE, tACE, or tAA.
5. To access RAM,
CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tAA is for RAM Address Access and tSAA is for Semaphore
Address Access.
6.
R/
W = VIH, CE = VIL, and OE = VIL. Address is valid prior to or coincident with CE transition Low.



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