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AD9802 датащи(PDF) 13 Page - Analog Devices |
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AD9802 датащи(HTML) 13 Page - Analog Devices |
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13 / 20 page ![]() AD9802 –13– REV. 0 Input Configurations Input JP1 JP2 JP3 JP4 JP5 JP8 JP9 JP10 Standard CCD Input J8 open short open open open open short open Grounded Input Test none open short open short open open short open Buffered Input* J9 open short open open short open short open Direct ADC Input J9 [ ... don’t care... ] short open short (9802 only) *When using the buffer amplifier, ±5 V must be connected to AVCC and AVSS, and R4 should be removed. Jumper Descriptions JP1 Connect to bypass the input coupling capacitor C18. JP2 Connect to short PIN and DIN (Pins 26 and 27 of the AD9801) together. JP3 Connects PIN to the dc level set by the wiper of R1. JP4 Connect to short the input coupling capacitor to ground, for test purposes. JP5 Connects the output of the buffer amplifier to the AD9801/AD9802 input. JP6 Connects the AD9801/AD9802’s DRVDD pin to the VDD supply through ferrite bead FB6. JP7 Connects the AD9801/AD9802’s DRVDD pin to the +3D supply. JP8 Connects the output of the AD8047 op amp to the direct ADC input of the AD9802. This jumper should never be connected on the AD9801-EB. JP9 Selects the regular camera mode of operation on the AD9802. This jumper should always be in place on the AD9801-EB. JP10 Selects the direct ADC input mode on the AD9802. This jumper should never be connected on the AD9801-EB. Test Point Descriptions TP1 Input signal at J8. TP2 Input signal at PIN/DIN of AD9801/AD9802. TP3 PGACONT1 voltage. TP4 PGACONT2 voltage. TP5 STANDBY pin, pull high to enable power-down mode. TP6 CLPDM at AD9801/AD9802. TP7 SHD at AD9801/AD9802. TP8 SHP at AD9801/AD9802. TP9 CLPOB at AD9801/AD9802. TP10 PBLK at AD9801/AD9802. TP11 ADCCLK at AD9801/AD9802. TP12 VDD TP13 AVCC TP14 AVSS TP15 AGND TP16 DGND TP17 +3D TP18 +3/5D Prototype Area The top left hole in the prototyping area is connected to AGND. The bottom right hole is connected to AVCC. OBSOLETE |
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