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ICS9248-138

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

General Description

Pin Configuration

The ICS9248-138 is the single chip clock solution for designs using the 810/810E and Solano style chipset. It provides all

necessary clock signals for such a system.

This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-138 employs a

proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.

PIN NU MBER

PIN NAME

TYPE

D ESCRIPTION

SEL24_48M H z#

IN

Logic inputs frequency select I/O /USB output,

When a "0" is latched, output frequency = 48M H z

When a "1" is latched, output frequency = 24M H z

REF0

O UT

14.318 M H z reference clock.

2, 10, 11, 18, 25,

30, 38

VDD

PWR

3.3V Pow er supply for SD RAM output buffers, PCI output buffers,

reference output buffers and 48M H z output

3

X 1

IN

Crystal input,nominally 14.318M H z.

4

X 2

O UT

Crystal output, nominally 14.318M Hz.

5, 6, 14, 21, 29, 34,

42

G N D

PWR

G round pin for 3V outputs.

9, 8, 7

3V 66 [2:0]

O UT

3.3V Clocks

FS 0

IN

Frequency select pin.

PCICLK 0

O UT

PCI clock output

FS 1

IN

Frequency select pin.

PCICLK 1

O UT

PCI clock output

20, 19, 17, 16, 15

PCICLK [6:2]

O UT

PCI clock outputs.

22

PD #

IN

A synchronous active low input pin used to power dow n the device into a low

power state. The internal clocks are disabled and the VCO and the crystal are

stopped. The latency of the pow er dow n w ill not be greater than 3ms.

23

SCLK

IN

Clock input of I2C input, 5V tolerant input

24

SD A TA

IN

D ata input for I2C serial input, 5V tolerant input

FS 4

IN

Frequency select pin.

48M H z

O UT

48M H z output clocks

FS 3

IN

Frequency select pin.

48M H z

O UT

48M H z output clocks

FS2

IN

Frequency select pin.

24_48M Hz

OUT

24 or 48M Hz output

31

SD RA M _F

O UT

Free running SD RA M - used for feed back to chipset, should remain on

alw ays.

32, 33, 35, 36, 37,

39, 40, 41,

SD RA M [7:0]

O UT

SD RA M clock outputs

43

GNDLCPU

PWR

Ground pin for the CPU clocks.

44, 45

CPU CLK [1:0]

O UT

CPU clock outputs.

46

VDDLCPU

PWR

Power pin for the CPUCLK s. 2.5V

47

IO A PIC

O UT

2.5V clock output

1

26

28

12

13

27