2

ICS9248-128

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Pin Descriptions

Notes:

1:

Internal Pull-up Resistor of 120K to 3.3V on indicated inputs

2:

Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor

to program logic Hi to VDD or GND for logic low.

P in num b er

P in nam e

T yp e

D escription

1

V DDR/X

P ower

Is olated 3.3 V power for c ry s tal & referenc e

RE F0

O utput

3.3V , 14.318 M Hz referenc e c loc k output.

M ode

Input

Func tion s elec t pin, 1= des k top m ode, 0= m obile m ode. Latc hed input.

3,9,16,22,

27,33,39

G ND

P ower

3.3 V Ground

4

X 1

Input

14.318 M Hz c ry s tal input

5

X 2

O utput

14.318 M Hz c ry s tal output

6,14

V DDP CI

P ower

3.3 V power for the P CI c loc k outputs

FS 1

Input

Logic input frequenc y s elec t bit. Input latc hed at power-on.

P CICLK _F

O utput

3.3 V free running P CI c loc k output, will not be s topped by the P CI_S TO P #

P CICLK 0

O utput

3.3 V P CI c loc k outputs , generating tim ing requirem ents for P entium II

FS 2

Input

Logic input frequenc y s elec t bit. Input latc hed at power-on.

13, 12, 11, 10

P CICLK (4:1)

O utput

3.3 V P CI c loc k outputs , generating tim ing requirem ents for P entium II

15,28,29,31,32,

34,35,37,38

SDRA M 12,

S DRA M (7:0)

O utput

S DRA M c loc k outputs . Frequenc y is s elec ted by S D-S el latc hed input.

S DRA M 11

O utput

S DRA M c loc k outputs . Frequenc y is s elec ted by S D-S el latc hed input.

CP U_S TOP #

Input

A s y nc hronous ac tiv e low input pin us ed to s top the CP UCLK in low s tate,

all other c loc k s will c ontinue to run. The CP UCLK will hav e a "Turnon" latenc y

of at leas t 3 CP U c loc k s .

S DRA M 10

O utput

S DRA M c loc k outputs . Frequenc y is s elec ted by S D-S E L latc hed input.

PCI-STO P #

Input

S y nc hronous ac tiv e low input us ed to s top the P CICLK in a low s tate. It will not

effec t P CICLK _F or any other outputs .

19

V DDS D/C

P ower

3.3 V power for S DRA M outputs and c ore

S DRA M 9

O utput

S DRA M c loc k outputs . Frequenc y is s elec ted by S D-S el latc hed input.

SDRA M_STOP #

Input

A s y nc hronous ac tiv e low input us ed to s top the S DRA M in a low s tate.

It will not effec t any other outputs .

S DRA M 8

O utput

S DRA M c loc k outputs . Frequenc y is s elec ted by S D-S el latc hed input.

P D#

Input

A s y nc hronous ac tiv e low input pin us ed to power down the dev ic e into a low

power s tate. The internal c loc k s are dis abled and the V CO and the c ry s tal are

s topped. The latenc y of the power down will not be greater than 3m s .

23

S DA TA

Input

24

S CLK

Input

S E L24_14#

Input

This input pin c ontrols the frequenc y of the S IO . If logic 0 at power on

S IO= 14.318 M Hz . If logic 1 at power-on S IO = 24M Hz .

S IO

O utput

S uper I/O output. 24 or 14.318 M Hz . S elec table at power-up by S E L24_14M Hz

FS 0

Input

Logic input frequenc y s elec t bit. Input latc hed at power-on.

48 M Hz

O utput

3.3 V 48 M Hz c loc k output, fix ed frequenc y c loc k ty pic ally us ed with

USB devic es

30,36

V DDS DR

P ower

3.3 V power for S DRA M outputs

40,41,43

CP UCLK (3:1)

0utput

2.5 V CP U and Hos t c loc k outputs

42

V DDLCP U

P ower

2.5 V power for CP U

RE F2

O utput

3.3V , 14.318 M Hz referenc e c loc k output.

CP U3.3#_2.5

Input

This pin s elec ts the operating v oltage for the CP U. If logic 0 at power on

CP U= 3.3 V and if logic 1 at power on CP U= 2.5 V operating v oltage.

45

GNDL

P ower

2.5 V Ground for the IOA P IC or CP U

RE F1

O utput

3.3V , 14.318 M Hz referenc e c loc k output.

S D_S E L#

Input

This input pin c ontrols the frequenc y of the S DRA M .

47

IOA P IC

O utput

2.5V fix ed 14.318 M Hz IO A P IC c loc k outputs

48

V DDLA P IC

P ower

2.5 V power for IOA P IC