2

ICS169C-232

Pin Descriptions

PIN NUM BER

PIN NAM E

TYPE

DESCRIPTIO N

1

VDD1

PWR

Power for control logic and crystal oscillator circuit and

14.318 M Hz output

2X1

IN

XTAL or external reference frequency input. This input includes XTAL

load capacitance and feedback bias for a 12-16MHz crystal, nominally

14.31818M Hz. External crystal load of 30pF to GND recommended for

VDD power on faster than 2.0ms.

3

X2

OUT

XTAL output which includes XTAL load capacitance. External crystal

load of 10pF to GND recommended for VDD power on faster than 2.0ms.

4,11,16,22

GND

PWR

Ground for control logic.

6,7,9,10,15

CPU(2,3,4,5,8)

OUT

Processor clock outputs which are a multiple of the input reference clock

as shown in the preceding table.

5,12,13

CP U1, CP U6,

CPU7

OUT

Processor clock outputs which are a multiple of the input reference clock

as shown in the preceding table.

5,12,13

FS (0:2)

IN

Frequency multiplier select pins. See shared pin programming description

later in this data sheet for further explanation. 350K* internal pull up.

8

VDD2

PWR

Power for CPU (1:6) clock buffers only. This VDD supply can be reduced

to 2.5V for CPU (1:6) outputs.

14

VDD3

PWR

Power for CPU (7:8) clock buffers and internal PLL and Core logic. Must

be nominal 3.3V (3.0 to 3.7V)

17,18,20,21,23, 24

BUS(1:6)

OUT

BUS clock outputs which are a multiple of the input reference clock as

shown in the preceding table.

19

VDD4

PWR

Power for BUS clock buffers BUS (1;6)

25

VDD5

PWR

Power for fixed clock buffer (48 MHz, 24 MHz)

26

24 MHz

OUT

Fixed 24 MHz clock (assuming a 14.31818 MHz REF frequency).

27

48 MHz

OUT

Fixed 48 MHz clock (assuming a 14.31818 MHz REF frequency).

28

REF

OUT

Fixed 14.31818 M Hz clock (assuming a 14.31818 MHz REF frequency).

BSEL

IN

Selection for synchronous or asynchronous bus clock operation. 350K*

internal pull up.

* The internal pull up will vary from 350K

to 500K based on temperature