2

ICS9150-02

Preliminary Product Preview

Pin Descriptions

Power Groups

VDD1 = REF (0:1), X1, X2

VDD2 = PCICLK_F, PCICLK (0:5)

VDD3 = SDRAM (0:12), Supply for PLL core

VDD4 = 48 MHz

VDDL1 = IOAPIC (0:1)

VDDL2 = CPUCLK (0:4)

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

2, 3

REF (0:1)

OUT

14.318 MHz reference clock outputs.

4, 10, 17, 23, 31,

34, 40, 47, 53

GND

PWR

Ground.

5X1

IN

14.318MHz input. Has internal load cap,(33pF).

6

X2

OUT

Crystal output. Has internal load cap (33pF) and feedback

resistor to X1

8

PCICLK_F

OUT

Free running BUS clock.

9, 11, 12, 13

14, 16

PCICLK (0:5)

OUT

BUS clock outputs.

18, 19

48MHz

OUT

48MHz clock outputs

21

N/C

-

Pins are not internally connected.

27

SDATA

IN

Serial data in for serial config port.

28

SCLK

IN

Clock input for serial config port.

29

OE

IN

Logic input for output enable, tristates all outputs when low.

30

SEL 66/60#

IN

Selects 60MHz or 66MHz for SDRAM and CPU.

1, 7, 15, 20, 26,

37, 43

VDD2, VDD1,

VDD3, VDD4

PWR

Nominal 3.3V power supply. See power groups for function.

50, 56

VDDL2, VDDL1

PWR

CPU and IOAPIC clock buffer power supply (2.5 - VDD)

22, 24, 25, 32, 33,

35, 36, 38, 39, 41,

42, 44, 45

SDRAM (0:12)

OUT

SDRAM clocks (60/66.6MHz)

54, 55

IOAPIC (1:0)

OUT

IOAPIC clock output. (14.31818 MHz) Powered by VDDL1

46, 48, 49, 51, 52

CPUCLK (0:4)

OUT

CPU Output clocks. Powered by VDDL2 (60 or 66.6MHz)