5

ICS9150-01

Serial Configuration Command Bitmaps

Byte 0: Functional and Frequency Select Clock Register (default = 0)

T

I

B#

N

I

PN

O

I

T

P

I

R

C

S

E

DD

W

P

7

ti

B-

d

e

v

r

e

s

e

R0

6

ti

B-

n

o

it

a

r

e

p

o

l

a

m

r

o

n

r

o

f

0

e

b

t

s

u

M0

5

ti

B

-n

o

it

a

r

e

p

o

l

a

m

r

o

n

r

o

f

0

e

b

t

s

u

M

0

-

e

p

y

t

s

l

o

r

t

n

o

C

,

m

u

r

t

c

e

p

S

d

a

e

r

p

S

n

I

)

d

a

e

r

p

s

n

w

o

d

=

1

,

d

e

r

e

t

n

e

c

=

0

(

4

ti

B

-n

o

it

a

r

e

p

o

l

a

m

r

o

n

r

o

f

0

e

b

t

s

u

M

0

-

s

l

o

r

t

n

o

C

s

l

o

r

t

n

o

C

,

m

u

r

t

c

e

p

S

d

a

e

r

p

S

n

I

%

g

n

i

d

a

e

r

p

S

)

%

6

.

0

=

1

,

%

8

.

1

=

0

(

3

ti

B-

d

e

v

r

e

s

e

R0

2

ti

B-

d

e

v

r

e

s

e

R0

1

ti

B

0

ti

B

-

1

ti

B

1

1

0

0

0

ti

B

e

t

a

t

S

-

i

r

T

-

1

e

l

b

a

n

E

m

u

r

t

c

e

p

S

d

a

e

r

p

S

-

0

e

d

o

m

t

s

e

T

-

1

n

o

i

t

a

r

e

p

o

l

a

m

r

o

N

-

0

0

0

General I

A.

an acknowledge bit between each byte.

B.

latches for verification. (set R/W# to 1 above). There is no BYTE count supported, so it does not meet the Intel SMB

PIIX4 protocol.

C.

The data transfer rate supported by this clock generator is 100K bits/sec (standard mode)

D.

The input is operating at 3.3V logic levels.

E.

The data byte format is 8 bit bytes.

F.

must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has

been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two

bytes. The data is loaded until a Stop sequence is issued.

G.

In the power down mode (PWR_DWN# Low), the SDATA and SCLK pins are tristated and the internal data latches

maintain all prior programming information.

H.

At power-on, all registers are set to a default condition. See Byte 0 detail for default condition, Bytes 1 through 5 default

to a 1 (Enabled output state)

Then Byte 0, 1, 2, etc in

sequence until STOP.

Byte 0, 1, 2, etc in sequence until STOP.

r

o

t

a

r

e

n

e

G

k

c

o

l

C

)

s

ti

b

7

(

s

s

e

r

d

d

A

K

C

A

y

m

m

u

d

s

ti

b

8

+

e

d

o

c

d

n

a

m

m

o

c

K

C

A

y

m

m

u

d

s

ti

b

8

+

t

n

u

o

c

e

t

y

B

K

C

A

#

W

/

R

&

)

0

:

6

(

A

2

D)

H

(

r

o

t

a

r

e

n

e

G

k

c

o

l

C

)

s

ti

b

7

(

s

s

e

r

d

d

A

K

C

A0

e

t

y

BK

C

A1

e

t

y

BK

C

A

#

W

/

R

&

)

0

:

6

(

A

3

D)

H

(

Note: PWD = Power-Up Default