74HC563N datasheet(2/7 Pages) PHILIPS

2 / 7 page

December 1990

Philips Semiconductors

Product speciﬁcation

Octal D-type transparent latch; 3-state;

inverting

74HC/HCT563

FEATURES

• 3-state inverting outputs for bus

oriented applications

• Inputs and outputs on opposite

sides of package allowing easy

interface with microprocessor

• Common 3-state output enable

input

• Output capability: bus driver

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT563 are high-speed

Si-gate CMOS devices and are pin

compatible with low power Schottky

TTL (LSTTL). They are specified in

compliance with JEDEC standard no.

7A.

The 74HC/HCT563 are octal D-type

transparent latches featuring

separate D-type inputs for each latch

and inverting 3-state outputs for bus

oriented applications.

A latch enable (LE) input and an

output enable (OE) input are common

to all latches.

The “563” is functionally identical to

the “573”, but has inverted outputs.

The “563” consists of eight D-type

transparent latches with 3-state

inverting outputs. The LE and OE are

common to all latches.

When LE is HIGH, data at the Dn

inputs enter the latches. In this

condition the latches are transparent,

i.e. a latch output will change state

each time its corresponding D-input

changes.

When LE is LOW the latches store the

information that was present at the

D-inputs a set-up time preceding the

HIGH-to-LOW transition of LE.

When OE is LOW, the contents of the

8 latches are available at the outputs.

When OE is HIGH, the outputs go to

the high impedance OFF-state.

Operation of the OE input does not

affect the state of the latches.

QUICK REFERENCE DATA

GND = 0 V; Tamb =25 °C; tr =tf = 6 ns

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

∑ (CL × VCC2 × fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2. For HC the condition is VI = GND to VCC

for HCT the condition is VI = GND to VCC − 1.5 V

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HCT

tPHL/ tPLH

propagation delay Dn, LE to Qn

CL = 15 pF; VCC =5 V

input capacitance

3.5

CPD

power dissipation capacitance per latch

notes 1 and 2

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