ICS670-01

Low Phase Noise Zero Delay Buffer and Multiplier

MDS 670-01 B

3

Revision 100900

Printed 11/15/00

Integrated Circuit Systems • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel•http://www.icst.com

Parameter

Conditions

Minimum

Typical

Maximum

Units

ABSOLUTE MAXIMUM RATINGS (n

note 1)

Supply voltage, VDD

Referenced to GND

7

V

Inputs and Clock Outputs

Referenced to GND

-0.5

VDD+0.5

V

Ambient Operating Temperature

0

70

°C

Ambient Operating Temperature, ICS670M-01I Industrial temperature

-40

85

°C

Soldering Temperature

Max of 10 seconds

260

°C

Storage temperature

-65

150

°C

DC CHARACTERISTICS (VDD = 3.3 V unless noted)

Operating Voltage, VDD

3.0

5.5

V

Input High Voltage, VIH

2

V

Input Low Voltage, VIL

0.8

V

Output High Voltage, VOH, CMOS level

IOH=-4mA

VDD-0.4

V

Output High Voltage, VOH

IOH=-12mA

2.4

V

Output Low Voltage, VOL

IOL=12mA

0.4

V

Operating Supply Current, IDD

No Load

35

mA

Short Circuit Current

Each output

±50

mA

Internal Pull-up Resistor

OE, select pins

200

k

Ω

Input Capacitance

OE, select pins

5

pF

AC CHARACTERISTICS (VDD = 3.3 V

V unless noted)

Input Frequency (see table on page 2)

Depends on multiplier

5

160

MHz

Output Frequency

at 3.3V or 5V

160

MHz

Output Clock Rise Time

0.8 to 2.0V, no load

1.5

ns

Output Clock Fall Time

0.8 to 2.0V, no load

1.5

ns

Output Clock Duty Cycle

At VDD/2

45

50

55

%

Input to output skew, rising edges

Note 2

±100

ps

Maximum Absolute Jitter, short term

±45

ps

Maximum Jitter, one sigma

15

ps

Phase Noise, relative to carrier, 125 MHz (x5)

100 Hz offset

-110

dBc/Hz

Phase Noise, relative to carrier, 125 MHz (x5)

1 kHz offset

-122

dBc/Hz

Phase Noise, relative to carrier, 125 MHz (x5)

10 kHz offset

-121

dBc/Hz

Phase Noise, relative to carrier, 125 MHz (x5)

100 kHz offset

-117

dBc/Hz

Electrical Specifications

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged

exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.

2. Rising edge of ICLK compared with rising edge of CLK2, with FBCLK connected to FBIN, and 15 pF load on CLK2.

See the graph on page 4 for skew versus frequency and loading.