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ICS1892Y-10 датащи(PDF) 125 Page - Integrated Circuit Systems

номер детали ICS1892Y-10
подробное описание детали  10Base-T/100Base-TX Integrated PHYceiver
PDF  148 Pages
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производитель  ICST [Integrated Circuit Systems]
домашняя страница  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS1892Y-10 датащи(HTML) 125 Page - Integrated Circuit Systems

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Chapter 10
DC and AC Operating Conditions
ICS1892, Rev. D, 2/26/01
February 26, 2001
125
ICS1892
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
10.5.2
Timing for Transmit Clock (TXCLK) Pin
Table 10-9 lists the significant time periods for signals on the Transmit Clock (TXCLK) pin for the various
interfaces. Figure 10-2 shows the timing diagram for the time periods.
Figure 10-2.
Transmit Clock Timing Diagram
Table 10-9.
Transmit Clock Timing
Time
Period
Parameter
Conditions
Min.
Typ.
Max.
Units
t1
TXCLK Duty Cycle
–
35
50
65
%
t2a
TXCLK Period
100M MII (100Base-TX)
–
40
–
ns
t2b
TXCLK Period
10M MII (10Base-T)
–
400
–
ns
t2c
TXCLK Period
100M Symbol Interface (100Base-TX)
–
40
–
ns
t2d
TXCLK Period
10M Symbol Interface (10Base-T)
–
100
–
ns
TXCLK
t1
t2x



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