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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ICS1892 датащи(PDF) 115 Page - Integrated Circuit Systems |
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ICS1892 датащи(HTML) 115 Page - Integrated Circuit Systems |
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115 / 148 page  Chapter 9 Pin Diagram, Listings, and Descriptions ICS1892, Rev. D, 2/26/01 February 26, 2001 115 ICS1892 © 2000-2001, Integrated Circuit Systems, Inc. All rights reserved. 9.2.4.3 MAC/Repeater Interface Pins for 10M Serial Interface Table 9-8 lists the MAC/Repeater Interface pin descriptions for the 10M Serial Interface. Table 9-8. MAC/Repeater Interface Pins: 10M Serial Interface MII Pin Name 10M Serial Pin Name Pin No. Pin Type Pin Description COL 10COL 49 Output 10M (Serial Interface) Collision (Detect). This pin’s description is the same as that given in Table 9-6. CRS 10CRS 50 Output 10M (Serial Interface) Carrier Sense. This pin’s description is the same as that given in Table 9-6. MDC MDC 31 Input Management Data Clock. This pin’s description is the same as that given in Table 9-6. MDIO MDIO 30 Input/ Output Management Data Input/Output. This pin’s description is the same as that given in Table 9-6. RXCLK 10RCLK 37 10M (Serial Interface) Receive Clock. This pin’s description is the same as that given in Table 9-6. RXCLK 10RCLK 37 10M (Serial Interface) Receive Clock. The 10RCLK pin name is the 10M Serial Interface mapping of the MII RXCLK (Receive Clock) pin name. The ICS1892 sources the 10RCLK to the MAC/repeater. The ICS1892 uses 10RCLK to synchronize the signals on the 10RD and 10RXDV pins. The following table contrasts the behavior on the 10RCLK pin when the mode for the ICS1892 is either 10Base-T or 100Base-TX. Note: The signal on the 10RCLK pin is conditioned by RXTRI. 10Base-T Serial The10RCLK frequency is 10 MHz. The ICS1892 generates 10RCLK from the MDI data stream using a digital PLL. When the MDI data stream terminates, the PLL continues to operate, synchronously referenced to the last packet received. The ICS1892 switches between clock sources during the period between when 10CRS is being asserted and 10RXDV is being asserted. While the ICS1892 locks onto the incoming data stream, a clock phase change of up to 360 degrees can occur. |
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