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Functional Description

The simplified block diagram below shows the 22-bit data

register, two 15-bit R Counters and the 15-bit and 18-bit N

Counters (intermediate latches are not shown). The data

stream is clocked (on the rising edge of Clock) into the

DATA input, MSB first. The last two bits are the Control

Bits. The DATA is transferred into the counters as follows:

CONTROL BITS

C1

C2

DATA LOCATION

0

0

IF R Counter

0

1

RF R Counter

1

0

IF N Counter

1

1

RF N Counter

Programmable Reference Dividers (IF and RF R Counters)

If the Control Bits are 00 or 01 (00 for IF and 01 for RF) data is transferred from the 22bit shift register into a latch which

sets the 15-bit R Counter. Serial data format is shown below.

15-Bit Programmable Reference Divider Ratio (R Counter)

DIVIDE

RRR

RRRR

RRRR

RRRR

RATIO

15

14

13

12

11

10

9

8765

4321

3

000

0000

0000

0011

4

000

0000

0000

0100

•

•••

••••

••••

••••

32767

1

1

1

1111

1111

1111

NOTES:

1. Divide ratios less than 3 are prohibited.

2. Divide ratio: 3 to 32767.

3. R1 to R15: These bits select the divide ratio of the programmable reference divider.

4. Data is shifted in MSB first.