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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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GMS81032 датащи(PDF) 68 Page - Hynix Semiconductor |
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GMS81032 датащи(HTML) 68 Page - Hynix Semiconductor |
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68 / 101 page  5 - 3 5.2 INTERRUPT CONTROL REGISTER I flag of PSW is a interrupt mask enable flag. When I flag = ¡È0¡È, all interrupts become disable. When I flag = ¡È1¡È, interrupts can be selectively enabled and disabled by contents of corresponding Interrupt Enable Register. When interrupt is occured, interrupt request flag is set, and Interrupt request is detected at the edge of interrupt signal. The accepted interrupt request flag is automatically cleared during interrupt cycle process. The interrupt request flag maintains ¡È1¡È until the interrupt is accepted or is cleared in program. In reset state, interrupt request flag register(IRQH, IRQL) is cleared to ¡È0¡È. It is possible to read the state of interrupt register and to mainpulate the contents of register and to generate interrupt. (Refer to software interrupt). - WDTR BITE - - - - - IENL R/W <00CCH> 7 0 Interrupt Enable Register Low KSCNE INT1E INT2E - T0E T1E T2E - IENH R/W <00CEH> 7 0 Interrupt Enable Register High - WDTR BITE - - - - - IRQL R/W <00CDH> 7 0 Interrupt Request Register Low KSCNR INT1R INT2R - T0R T1R T2R - IRQH R/W <00CFH> 7 0 Interrupt Request Register High Chapter 5. Interrupt |
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