ATXMEGA8E5_14 datasheet(28/147 Pages) ATMEL

28 / 147 page

XMEGA E5 [DATASHEET]

Atmel-8153I–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–08/2014

15.

Interrupts and Programmable Multilevel Interrupt Controller

15.1

Features

Short and predictable interrupt response time

Separate interrupt configuration and vector address for each interrupt

Programmable multilevel interrupt controller

Interrupt prioritizing according to level and vector address

Three selectable interrupt levels for all interrupts: low, medium and high

Selectable, round-robin priority scheme within low-level interrupts

Non-maskable interrupts for critical functions

Interrupt vectors optionally placed in the application section or the boot loader section

15.2

Overview

Interrupts signal a change of state in peripherals, and this can be used to alter program execution. Peripherals can have

one or more interrupts, and all are individually enabled and configured. When an interrupt is enabled and configured, it

will generate an interrupt request when the interrupt condition is present. The programmable multilevel interrupt

controller (PMIC) controls the handling and prioritizing of interrupt requests. When an interrupt request is acknowledged

by the PMIC, the program counter is set to point to the interrupt vector, and the interrupt handler can be executed.

All peripherals can select between three different priority levels for their interrupts: low, medium, and high. Interrupts are

prioritized according to their level and their interrupt vector address. Medium-level interrupts will interrupt low-level

interrupt handlers. High-level interrupts will interrupt both medium- and low-level interrupt handlers. Within each level, the

interrupt priority is decided from the interrupt vector address, where the lowest interrupt vector address has the highest

interrupt priority. Low-level interrupts have an optional round-robin scheduling scheme to ensure that all interrupts are

serviced within a certain amount of time.

Non-maskable interrupts (NMI) are also supported, and can be used for system critical functions.

15.3

Interrupt vectors

The interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for specific interrupts in

each peripheral. The base addresses for the Atmel AVR XMEGA E5 devices are shown in Table 15-1. Offset addresses

for each interrupt available in the peripheral are described for each peripheral in the XMEGA AU manual. For peripherals

or modules that have only one interrupt, the interrupt vector is shown in Table 15-1. The program address is the word

address.

Table 15-1. Peripheral module address map

Program address

(base address)

Source

Interrupt Description

0x0000

RESET

0x0002

OSCF_INT_vect

Crystal oscillator failure and PLL lock failure interrupt vector (NMI)

0x0004

PORTR_INT_vect

Port R Interrupt vector

0x0006

EDMA_INT_base

EDMA Controller Interrupt base

0x000E

RTC_INT_base

Real time counter interrupt base

0x0012

PORTC_INT_vect

Port C interrupt vector

0x0014

TWIC_INT_base

Two-wire interface on Port C interrupt base

ATXMEGA8E5 датащи(PDF) 28 Page - ATMEL Corporation

ATXMEGA8E5 датащи(HTML) 28 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL