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A7985ATR датащи(PDF) 22 Page - STMicroelectronics |
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A7985ATR датащи(HTML) 22 Page - STMicroelectronics |
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22 / 44 page ![]() Application information A7985A 22/44 DocID023128 Rev 5 6.4.1 Type III compensation network The methodology to stabilize the loop consists in placing two zeroes to compensate the effect of the LC double pole, thereby increasing phase margin; then to place one pole in the origin to minimize the DC error on the regulated output voltage; finally to place other poles far from the zero dB frequency. If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a frequency higher than the desired bandwidth (that is: 2 ESR COUT < 1 / BW), the Type III compensation network is needed. Multi-layer ceramic capacitors (MLCC) have very low ESR (< 1 m ), with very high frequency zero, so a Type III network is adopted to compensate the loop. In Figure 10, the Type III compensation network is shown. This network introduces two zeroes (fZ1, fZ2) and three poles (fP0, fP1, fP2). They are expressed as: Equation 23 Equation 24 Figure 10. Type III compensation network fZ1 1 2 C 3 R1 R3 + ------------------------------------------------ = fZ2 1 2 R 4 C4 ------------------------------ = fP0 0 = fP1 1 2 R 3 C3 ------------------------------ = fP2 1 2 R 4 C4 C5 C4 C5 + -------------------- -------------------------------------------- = |
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