1-174

Package Characteristics

Parameter

Sym.

Package*

Min.

Typ.

Max.

Units

Test Conditions

Fig.

Note

Input-Output

2500

V rms

RH

≤ 50%,

5, 6

Momentary With-

t = 1 min.,

stand Voltage**

Input-Output

Ω

4, 8

Resistance

Input-Output

0.6

pF

f = 1 MHz,

4, 8

Capacitance

Input-Input

Dual Channel

0.005

µA

RH

≤ 45%,

19

Insulation

t = 5 s,

Leakage Current

Resistance

Dual Channel

Ω

19

(Input-Input)

Capacitance

Dual 8-pin DIP

0.03

pF

f = 1 MHz

19

Dual SO-8

0.25

*Ratings apply to all devices except otherwise noted in the Package column.

**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output

continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable),

your equipment level safety specification or HP Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage.”

†For 8-pin DIP package devices (HCPL-261A/261N/263A/263N) only.

(Input-Input)

OPT 020†

5000

5, 7

Notes:

1. Peaking circuits may be used which

produce transient input currents up

to 30 mA, 50 ns maximum pulse

width, provided the average current

does not exceed 10 mA.

2. 1 minute maximum.

3. Derate linearly above 80

°C free-air

temperature at a rate of 2.7 mW/

°C

for the SOIC-8 package.

4. Each channel.

5. Device considered a two-terminal

device: Pins 1, 2, 3, and 4 shorted

together and Pins 5, 6, 7, and 8

shorted together.

6. In accordance with UL1577, each

optocoupler is proof tested by

applying an insulation test voltage

≥ 3000 V

This test is performed before the

100% production test for partial

discharge (method b) shown in the

VDE 0884 Insulation Characteristics

Table, if applicable.

7. In accordance with UL1577, each

optocoupler is proof tested by

applying an insulation test voltage

≥ 6000 V

8. Measured between the LED anode and

cathode shorted together and pins 5

through 8 shorted together.

measured from the 1.75 mA point on

the falling edge of the input pulse to

the 1.5 V point on the rising edge of

the output pulse.

measured from the 1.75 mA point on

the rising edge of the input pulse to

the 1.5 V point on the falling edge of

the output pulse.

equal to the worst case difference in

between any two units under the

same test conditions and operating

temperature.

12. Single channel products only (HCPL-

261A/261N/061A/061N).

13. Common mode transient immunity in

a Logic High level is the maximum

output will remain in a Logic High

state (i.e., Vo > 2.0 V).

14. Common mode transient immunity in

a Logic Low level is the maximum

output will remain in a Logic Low

15. For sinusoidal voltages

16. Bypassing of the power supply line is

required with a 0.1

µF ceramic disc

capacitor adjacent to each optocoup-

ler as shown in Figure 19. Total lead

length between both ends of the

capacitor and the isolator pins should

not exceed 10 mm.

17. Pulse Width Distortion (PWD) is

defined as the difference between

18. No external pull up is required for a

high logic state on the enable input of

in improved CMR performance.

19. Measured between pins 1 and 2

shorted together, and pins 3 and 4

shorted together. For dual channel

parts only.