Pin Description

Pin Name I/O

Internal

Connection

Description

VP

I OPERATIONAL

AMPLIFIER

Operational amplifier non-inverting input

VN

I

Operational amplifier inverting input

GS

O

Operational amplifier output terminal

VREF

O

VREF

X1

I

OSCILLATOR

The system oscillator consists of an inverter, a bias resistor

and the necessary load capacitor on chip.

A standard 3.579545MHz crystal connected to X1 and X2 ter-

minals implements the oscillator function.

X2

O

PWDN

I

CMOS IN

Pull-low

Active high. This enables the device to go into power down

mode and inhibits the oscillator. This pin input is internally

pulled down.

INH

I

CMOS IN

Pull-low

Logic high. This inhibits the detection of tones representing

characters A, B, C and D. This pin input is internally pulled

down.

VSS

¾¾

Negative power supply

OE

I

CMOS IN

Pull-high

D0~D3 output enable, high active

D0~D3

O

CMOS OUT

Tristate

Receiving data output terminals

OE=²H²: Output enable

OE=²L²: High impedance

DV

O

CMOS OUT

Data valid output

When the chip receives a valid tone (DTMF) signal, the DV

goes high; otherwise it remains low.

EST

O

CMOS OUT

Early steering output (see Functional Description)

RT/GT

I/O CMOS IN/OUT Tone acquisition time and release time can be set through

connection with external resistor and capacitor.

VDD

¾¾

Positive power supply, 2.5V~5.5V for normal operation

DVB

O

CMOS OUT

One-shot type data valid output, normal high, when the chip

receives a valid time (DTMF) signal, the DVB goes low for

10ms.

HT9170

3

December 20, 1999