HT827A0 datasheet(21/49 Pages) HOLTEK

21 / 49 page

HT827A0

March 15, 2000

TMRH will write the data and the content of the

low byte buffer into the timer/event counter

preload register (16-bit) simultaneously. The

timer/event counter preload register is changed

by writing TMRH operations and writing TMRL

will keep the timer/event counter preload register

unchanged.

Reading TMRH will also latch the TMRL into

the low byte buffer to avoid the false timing

problem. Reading TMRL returns the content of

the low byte buffer. In other words, the low byte

of the timer/event counter can not be read di-

rectly. It must read the TMRH first to make the

low byte content of the timer/event counter

latched into the buffer.

For the 8-bit timer/event counter, TMRH is unde-

fined. Writing TMRL makes the starting value be

placed in the timer/event counter preload register

and reading it gets the contents of the

timer/event counter. TMRC is a timer/event

counter control register which defines some op-

tions.

The TM0 and TM1 bits define the operation

mode. The event counting mode counts external

events, indicating that the source of the clock is

from an external (TMR) pin. The timer mode

functions as a normal timer with the clock

source coming from an instruction clock. The

pulse width measurement mode can be used to

count a high to low level duration of an external

signal (TMR). This counting is based on the in-

struction clock.

In the event counting or timer mode, after the

timer/event counter starts counting, it will count

from its current contents to FFFFH for 16-bit

timer/event counter or FFH for 8-bit timer/event

counter. Once an overflow occurs, the counter is

reloaded from the timer/event counter preload

(TF; bit 6 of INTC).

In the pulse width measurement mode with the

TON and TE bits equal to one, after TMR tran-

sition from low to high (or high to low when the

TE bit is ²0²), it will start counting till it returns

to the original level and resets the TON. The

measured result still remains in the

timer/event counter even when the activated

transition re-occurs. In other words, only one

cycle can be measured till TON is set. The cycle

measurement will go on functioning as long as

further transient pulses are received. In this

operation mode, the timer/event counter starts

counting not according to the logic level but to

the transient edges. In the case of a counter

overflow, the counter is reloaded from the

timer/event counter preload register and issues

an interrupt request, like the other two modes.

The timer ON bit (TON; bit 4 of TMRC) should

be set to 1 to enable a counting operation. In the

pulse width measurement mode, TON will be

cleared automatically after the measurement

cycle is completed. In the other two modes,

TON can be reset only by instructions. The

overflow of the timer/event counter is one of the

wake-up sources. Writing a ²0² to ETI will dis-

able the interrupt service no matter what kind

of operation mode is chosen.

In the case of the timer/event counter OFF con-

dition, writing data to the timer/event counter

preload register will also reload it to the

timer/event counter. Data written to the

timer/event counter will however be kept in the

timer/event counter preload register if the

timer/event counter is turned on. It will keep on

operating till an overflow occurs.

The clock will be blocked to avoid errors when

the timer/event counter (reading TMR) is read.

The programmer should take the counting er-

ror into account since clock blocking may result

in a counting error.

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