When set, this bit causes the IRQ signal to be asserted if a parity error is detected.

When set, this bit causes the IRQ signal to be asserted if EOP is received from the DMA controller.

When set, this bit causes the IRQ signa asserted when BSY changes to the inactive state for at

least a bus settle delay.

When set, this bit starts the arbitration process.

Address 3: Target command register

7

6

5

4

3

2

1

0

LAST BYTE

X

X

X

ASSERT

REQ

ASSERT

MSG

ASSERT

C/D

ASSERT

I/O

R

R/W

R/W

R/W

R/W

WHEN SET, THE REQ SIGNAL IS ASSERTED ON THE SCSI BUS (IN TARGET MODE)

WHEN SET, THE MSG SIGNAL IS ASSERTED ON THE SCSI BUS (IN TARGET MODE)

WHEN SET, THE C/D SIGNAL IS ASSERTED ON THE SCSI BUS (IN TARGET MODE)

WHEN SET, THE I/O SIGNAL IS ASSERTED ON THE SCSI BUS (IN TAGRTE MODE)

Address 4: Current SCSI Bus Register

READ

7

6

5

4

3

2

1

0

RST

BSY

REQ

MSG

C/D

I/O

SEL

DBP

WRITE

–SELECT ENABLE REGISTER

7

6

5

4

3

2

1

0

SID7

SID6

SID5

SID4

SID3

SID2

SID1

SID0

HT6576A

5

14th July ’97