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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HT24LC02 датащи(PDF) 4 Page - Holtek Semiconductor Inc |
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HT24LC02 датащи(HTML) 4 Page - Holtek Semiconductor Inc |
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4 / 8 page  Functional Description • Serial clock (SCL) The SCL input is used for positive edge clock data into each EEPROM device and negative edge clock data out of each device. • Serial data (SDA) The SDA pin is bidirectional for serial data transfer. The pin is open-drain driven and may be wired-OR with any number of other open-drain or open collector devices. • A0, A1, A2 The A2, A1 and A0 pins are device address inputs that are hard wired for the HT24LC01/02. As many as eight 1K/2K de- vices may be addressed on a single bus system (the device addressing is discussed in detail under the Device Addressing section). • Write protect (WP) The HT24LC01/02 has a write protect pin that provides hardware data protection. The write protect pin allows normal read/write operations when connected to the VSS. When the write protect pin is connected to Vcc, the write protection feature is enabled and oper- ates as shown in the following table. WP Pin Status Protect Array HT24LC01 HT24LC02 At VCC Full Array (1K) Full Array (2K) At VSS Normal Read/Write Operations Memory organization • HT24LC01, 1K Serial EEPROM Internally organized with 128 8-bit words, the 1K requires a 7-bit data word address for random word addressing. • HT24LC02, 2K Serial EEPROM Internally organized with 256 8-bit words, the 2K requires an 8-bit data word address for random word addressing. Device operations • Clock and data transition Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in data line while the clock line is high will be interpreted as a START or STOP condition. • Start condition A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Defi- nition Timing diagram). • Stop condition A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition Timing Diagram). • Acknowledge All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknow- ledge that it has received each word. This happens during the ninth clock cycle. Device addressing The 1K and 2K EEPROM devices all require an 8-bit device address word following a start con- dition to enable the chip for a read or write operation. The device address word consist of a mandatory one, zero sequence for the first four most significant bits (refer to the diagram show- ing the Device Address). This is common to all the EEPROM device. The next three bits are the A2, A1 and A0 device address bits for the 1K/2K EEPROM. These three bits must compare to their corresponding hard-wired input pins. HT24LC01/02 4 6th May ’99 |
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