Pin Assignment

Pin Description

Pin Name I/O

Internal

Connection

Description

A0~A7

I

CMOS IN

Pull-high

(HT12A)

Input pins for address A0~A7 setting

These pins can be externally set to VSS or left open

NMOS

TRANSMISSION

GATE

PROTECTION

DIODE

(HT12E)

AD8~AD11

I

NMOS

TRANSMISSION

GATE

PROTECTION

DIODE

(HT12E)

Input pins for address/data AD8~AD11 setting

These pins can be externally set to VSS or left open

D8~D11

I

CMOS IN

Pull-high

Input pins for data D8~D11 setting and transmission en-

able, active low

These pins should be externally set to VSS or left open

(see Note)

DOUT

O

CMOS OUT

Encoder data serial transmission output

L/MB

I

CMOS IN

Pull-high

Latch/Momentary transmission format selection pin:

Latch: Floating or VDD

Momentary: VSS

HT12A/HT12E

3

April 11, 2000

8- A d d r ess

4- D a t a

A0

A1

A2

A3

A4

A5

A6

A7

VS S

VD D

DO UT

X1

X2

L/ M B

D1 1

D1 0

D9

D8

1

2

3

4

5

6

7

8

9

18

17

16

15

14

13

12

11

10

8- A d d r ess

4- D a t a

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

NC

VD D

DO UT

X1

X2

L/ M B

D1 1

D1 0

D9

D8

NC

A0

A1

A2

A3

A4

A5

A6

A7

VS S

HT 1 2 A

18 D I P

HT 1 2 A

20 S O P

8- A d d r ess

4- A d d r ess/ D a t a

A0

A1

A2

A3

A4

A5

A6

A7

VS S

VD D

DO U T

OS C 1

OS C 2

TE

AD 1 1

AD 1 0

AD 9

AD 8

1

2

3

4

5

6

7

8

9

18

17

16

15

14

13

12

11

10

H T 1 2 E

1 8 D I P

8- A d d r ess

4- A d d r ess/ D a t a

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

NC

VD D

DO U T

OS C 1

OS C 2

TE

AD 1 1

AD 1 0

AD 9

AD 8

NC

A0

A1

A2

A3

A4

A5

A6

A7

VS S

H T 1 2 E

2 0 S O P